poly-Si TFTs Research Articles

Characterizations of polycrystalline silicon nanowire thin-film transistors enhanced by metal-induced lateral crystallization

In this paper, we present a comprehensive study on the effects of layout design and re-crystallization temperature on the material and electrical characteristics of polycrystalline silicon thin-film transistors (poly-Si TFTs) with metal-induced lateral crystallized (MILC) nanowire (NW) channels. It is found that the off-state leakage current shows strong dependence on the arrangement of MILC seeding windows, while the number of smaller solid-phase-crystallized (SPC) grains in the channel is reduced by lowering the re-crystallization temperature, thus improving the on-state behavior. Moreover, owing to the spatial confinement for MILC fronts, small cross-section of the NW channel would result in little lateral crystallization, and thus retarding the enhancement in performance of MILC NW devices.

Degradation of p-Channel Low Temperature Poly-Si TFTs with Positive Source Pulse Stress

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Hydrogen Instability Induced by Postannealing on Poly-Si TFTs

This brief investigates hydrogen instability induced by postannealing. Results show that using a SiN capping layer can prevent the release of hydrogen from a polycrystalline-silicon channel. However, removing this SiN capping layer allows the hydrogen release during postannealing, and the resulting device performance becomes comparable to that of the control sample. Hydrogen release reduces the immunity of PBTI and NBTI. Two possible mechanisms can explain the increased preexisting defects associated with hydrogen release, which affects the NBTI and PBTI.

P‐9: Bridged Grain MIC Poly‐Si Thin‐Film Transistors with Sputtered AlOx as Gate Dielectrics

AbstractBridged grain (BG) technology was applied to fabricate MIC poly‐Si TFTs with AlOx gate dielectrics. The threshold voltage (Vth) and subthreshold swing (SS) of MIC TFTs are greatly improved. Meanwhile, the drawback of using high‐k dielectrics, such as large off‐state leakage current and early kink effect was effectively suppressed by using BG structure. Combination of BG and high‐k gate insulators makes the resulting device a promising candidate for system on panel applications.

Growth of very large grains in polycrystalline silicon thin films by the sequential combination of vapor induced crystallization using AlCl3 and pulsed rapid thermal annealing

Metal-induced crystallization method is one of the favorable non-laser crystallization methods for thin-film transistors in large-area displays. However, it is necessary to reduce metal contamination in the film to lower leakage current for the device applications. A new two-step crystallization method, consisting of a nucleation step by AlCl3 vapor-induced crystallization and a grain growth step by a pulsed rapid thermal annealing, has been proposed to increase the grain size and reduce the residual metal contamination in crystallized poly-Si films. The grain size of the poly-Si film crystallized by the VIC + PRTA two-step crystallization process was as large as 70 μm. Furthermore, the Al concentration in the poly-Si film was reduced by two orders of magnitude from 1 × 1020 cm−3 by VIC only process to 1.4 × 1018 cm−3 by the two-step process. As a result, the minimum leakage current of poly-Si TFTs using the poly-Si film prepared by the two-step process was reduced from 1.9 × 10−10 A/μm to 2.8 × 10−11 A/μm at a drain voltage of 5 V, without carrier mobility degradation.

A Novel Lightly Doping Technique for LDD Structure MILC Poly-Si TFTs Using Gate Insulator as a Doping Mask and the Effect of the LDD Structure on the TFTs

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Hot-Carrier Effects in Short Channel (L = 1.5 µm) p-Type Polycrystalline Silicon Thin-Film Transistors

We have investigated the reliability of short-channel (L = 1.5 µm) p-type excimer-laser-annealed (ELA) polycrystalline silicon (poly-Si) TFTs under hot-carrier related static bias stress. The threshold voltage (ΔVTH = 0.59 V) of short-channel TFTs (L = 1.5 µm) was significantly more shifted to the positive direction than that (ΔVTH = 0.02 V) of long-channel TFTs (L = 7 µm) under the same stress condition for 100 s. This positive shift of threshold voltage may be attributed to electron trapping at the interface between the poly-Si film and the gate oxide layer. In addition, we have extracted the length of the drain extension from an equation of the pseudo-lightly doped drain (LDD) model to verify the existence of free hole charges induced near the drain junction. The transfer characteristics of the normal and drain-source swapped modes as well as the capacitance–voltage (C–V) characteristics with variation in channel length after the bias stress indicate that the electron trapping at the gate insulator/channel interface mainly occurred near the drain junction region. Furthermore, the threshold voltage of the short-channel ELA poly-Si TFTs with L = 1.5 µm was largely increased as the stress temperature was increased from room temperature to 100 °C, which indicates that the impact ionization occurs more at higher temperature.

저온 다결정 실리콘 박막 트랜지스터의 비정상적인 Hump 현상 분석

In this paper, we investigated an anomalous hump phenomenon under the positive bias stress in p-type LTPS TFTs. The devices with inferior electrical performance also show larger hump phenomenon. which can be explained by the sub-channel induced from trapped electrons under thinner gate oxide region. We can confirm that the devices with larger hump have larger interface trap density (<TEX>$D_{it}$</TEX>) and grain boundary trap density (<TEX>$N_{trap}$</TEX>) extracted by low-high frequency capacitance method and Levinson-Proano method, respectively. From the C-V with I-V transfer characteristics, the trapped electrons causing hump seem to be generated particularly from the S/D and gate overlapped region. Based on these analysis, the major cause of an anomalous hump phenomenon under the positive bias stress in p-type poly-Si TFTs is explained by the GIDL occurring in the S/D and gate overlapped region and the traps existing in the channel edge region where the gate oxide becomes thinner, which can be inferred by the fact that the magnitude of the hump is dependent on the average trap densities.

Reducing OLED Degradation Using Self-Compensated Circuit for AMOLED Displays

In this letter, the electric characteristics of the fabricated organic light-emitting diode (OLED) devices are analyzed after a bias stress. Experimental results demonstrate that when a constant voltage is applied to the OLED device, the OLED threshold voltage gradually increases, resulting in the driving current to decay. Therefore, a novel voltage driving scheme for active-matrix OLEDs using low-temperature polysilicon thin-film transistors (poly-Si TFTs) is proposed. This circuit uses three TFTs to increase the aperture ratio of panels and the driving current of the OLED device to ameliorate the luminance drop that is caused by OLED degradation. Simulation results indicate that the proposed pixel circuit has high immunity to VTH variations of the poly-Si TFTs and provides an extra compensation current against OLED degradation.

An Analytical Subthreshold Model for Polysilicon Thin-Film Transistors by a Quasi-Two-Dimensional Solution

An analytical expression of the surface potential for polysilicon thin-film transistors (poly-Si TFTs) working in the subthreshold region is obtained, following a quasi-2-D Poisson's equation, and then, an analytical subthreshold current model is subsequently developed based on the processes of diffusion and thermal emission. Furthermore, the kink effect is also taken into account in the subthreshold current model. Consequently, an analytical expression of the subthreshold swing is obtained from the surface potential equation and the subthreshold current expression. It is easily shown in our model that the subthreshold swing of poly-Si TFTs decreases with reducing the trap states or enlarging the grain size, and then, the switching performance of poly-Si TFTs will be improved. Moreover, this model has a simple functional form, and it can reduce to that of the conventional long-channel MOSFET in the case of large grain size and low trap states. The model has been verified by comparing simulated results with experimental data.

Interface diffusion characteristics of Al–2 at.%Nd/n + a-Si:H and Al–2 at.%Nd/n + poly-Si bilayers

In order to use Al–2 at.%Nd as the source-drain electrode of hydrogenated amorphous silicon thin film transistors (a-Si:H TFTs) without diffusion barrier, the diffusion characteristics of Al–2 at.%Nd into phosphorus-doped (n+) a-Si:H were studied, and diffusion between Al–2 at.%Nd and phosphorous-doped poly-Si (n + poly-Si) was also investigated for comparison. The electric resistance variation of Al–2 at.%Nd, n + a-Si:H, and n + poly-Si was measured by four-point probe method at every annealing step, and each surface was inspected by optical microscope. Auger Electron Spectroscopy and X-ray Photoelectron Spectroscopy were used to analyze atomic diffusion progress with the variation of annealing temperature. Through these analyses, we ascertain that the Nd element of Al–2 at.%Nd hinders the diffusion between Al and Si, and n + a-Si:H is stable up to 300 °C and n + poly-Si is stable up to 400 °C against the diffusion of Al–2 at.%Nd. Thus Al–2 at.%Nd can be utilized as the source-drain electrode of a-Si:H TFTs below 300 °C and poly-Si TFTs below 400 °C without diffusion barrier.

Bias-Temperature- and Light-Induced Instability in Short-Channel (L = 1.5 µm) p-Type Polycrystalline Silicon Thin-Film Transistors on Glass Substrates

We investigated the electrical al characteristics of laser-crystallized polycrystalline silicon thin-film transistors (poly-Si TFTs) under various stresses, such as bias, temperature, and light illumination. The threshold voltage of the short-channel TFTs (LCH = 1.5 µm) was significantly shifted in the negative direction owing to bias temperature stress (ΔVTH = -3.75 V) compared with that found in long-channel TFTs (ΔVTH = -0.32 V) at 100 °C. We also investigated the effects of light illumination on laser-crystallized poly-Si TFTs. In order to improve the reliability of laser-crystallized poly-Si TFTs, we developed a multiple-channel structure fabricated without using any additional processes.

Passivation-Induced Subthreshold Kink Effect of Ultrathin-Oxide Low-Temperature Polycrystalline Silicon Thin Film Transistors

Polycrystalline silicon thin-film transistors (poly-Si TFTs) with an ultrathin electron cyclotron resonance plasma-oxidized gate oxide have been fabricated. These ultrathin gate oxide poly-Si TFTs demonstrate better gate controllability and short-channel effect suppression, as compared with conventional thick-gate oxide poly-Si TFTs. A subthreshold kink effect has been observed in these ultrathin gate oxide poly-Si TFTs after NH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> plasma treatment for the first time. The ultrathin oxide will limit the diffusion of plasma radicals, resulting in plasma radical pileup along the channel width, causing this subthreshold kink effect. The kink effect will be less significant in devices with a narrow channel width as the current flow associated with the corners of the device will dominate over the flat-plate region.

MILC PMOS Poly-Silicon TFT Circuits and Application in SOP

Research towards thin film circuits is one of the most attractive directions of the large-area electronics and flexible electronics. In this work, the research on TFT shift register circuit which is critical for system integration on panel (SOP) is presented. The whole circuit is composed of MILC PMOS poly-Si TFTs. The TFT device exhibited field-effect mobility of 65.21cm2/Vs, threshold voltage of -3.5V and sub-threshold swing of 0.56V/dec. Some special design considerations were adopted to improve the robustness of the circuits. The whole shift register is composed of as many as 180 stages and exhibited well performance with frame frequency from 22Hz to 220Hz at the power supply voltage of 11V. No signal attenuation and distortion appeared from the first to the final stage. The effect of bootstrapping and dynamic behavior is analyzed. The fabrication and reliability analysis are also discussed in this paper. Overall, the high performance driver circuits based on our MILC PMOS process are possible and have the potential in the application of SOP.

Thin-BOX Poly-Si Thin-Film Transistors for CMOS-Compatible Analog Operations

This paper presents device models and optimization methodology for reducing short-channel effects in low-temperature polycrystalline-silicon thin-film transistors (LTPS TFTs), which are suitable for standard complementary metal-oxide-semiconductor (CMOS)-compatible analog operations. We analyze channel-length modulation to determine appropriate channel length having a single grain boundary in the channel fabricated using excimer laser-annealed crystallization under low-temperature constraint. Furthermore, buried-oxide-induced barrier lowering (BIBL) is investigated in poly-Si TFTs. BIBL makes the effective channel length shorter, resulting in difficulty to use LTPS TFTs for analog applications due to small output resistance rout. We show that, with scaling of the buried-oxide (BOX) thickness Tbox and an appropriate channel length, rout and the normalized transconductance gm/Id (with Tbox = 10 nm) can be improved by 103% and 8%, respectively, compared with thicker BOX (Tbox = 50 nm). In addition, due to the decrease in leakage currents, the Ion/Ioff ratio of the thin-BOX device can be three times larger than that of the thicker BOX device. Based on the process-constrained optimized device, we designed a 417-μW 65-dB folded-cascode operational amplifier with 2-V supply for CMOS-compatible operations.

Hydrogen passivation on Sequential Lateral Solidified poly-Si TFTs

The field effect mobility is sufficiently and impressively improved by increasing the passivation time from 15min to 50min, denoting that SLS films allow quite efficient passivation of defects. The present work investigates the effects of hydrogen passivation on the electrical performance of Sequential Lateral Solidified (SLS) poly-Si TFTs by analyzing the dependence of electrical properties on temperature. Under hydrogenation the density of states in the band gap is sufficiently reduced. Analysis of the thermally activated parameters reveals that although previous studies suggest poor passivation of tail states, in SLS TFTs the passivation rate is significantly improved. Moreover, devices subjected to hydrogenation for a longer time exhibit a higher threshold temperature for the thermally activated mechanisms and a lower threshold voltage temperature shift (ΔVT). It is also found that mobility is almost doubled, which taken into account that previously reported values in laser crystallized films are of the order of 10%, is quite a notable result.

Hysteresis suppression improvement of polycrystalline silicon thin-film transistors by two-step hydrogenation

The effect of two-step hydrogenation, consisting of plasma hydrogenation and annealing in hydrogen, on the hysteresis phenomenon of metal-induced unilaterally crystallized silicon thin-film transistors (MIUC-Si TFTs) was investigated. The large hysteresis level of the conventional MIUC-Si TFTs caused a wide variation of the drain current with the previous gate voltage. As the plasma exposure time increased, the plasma hydrogenation commonly used for stability in poly-Si TFTs was found to increase the hysteresis level of MIUC-Si TFTs after a minimum point. This is because plasma-induced damages correlated with unique defects of MIUC-Si such as metal-related weak bonds, are accompanied by passivation. The following annealing repaired the damages. Consequently the hysteresis level was lower, which resulted in a narrower variation of the drain current.

Thermally generated leakage current mechanisms of metal-induced laterally crystallized n-type poly-Si TFTs under hot-carrier stress

Mechanisms of thermally generated leakage current have been systematically studied for metal-induced laterally crystallized n-type polycrystalline silicon thin film transistors under the hot-carrier stress. Various mechanisms of thermally generated leakage current are identified by both forward and reverse modes. The decrease of thermally generated leakage current is attributed to the depletion region modulation effect, which results from its shrinkage. While the increase of thermally generated leakage current is caused by the increase of the donor trap density, its increment relative to the initial one follows the Schottky model in the forward mode. Overall, the depletion region modulation effect dominates and the thermally generated leakage current decreases.

Generalized Hot-Carrier Degradation and Its Mechanism in Poly-Si TFTs Under DC/AC Operations

In the previous report, we had reported the mechanism for the degradation of poly-Si TFTs under OFF region gate ac operation with the source and drain electrodes grounded. In this paper, the study is extended to the degradation of the devices under various ac and dc operation conditions. It is discovered that, though these stress conditions are different, the corresponding degradation behaviors in their <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</i> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> curves all resemble the degradation behavior of the device under dc hot-carrier stress. Two important factors, namely, the electric field across the junction and the number of carriers flowing through the junction, are taken into discussion in this paper and comparison of these stress conditions. It is then categorized that these operation conditions can be described as the “generalized hot-carrier effect,” since the degradation is found to occur near the junctions by the energized carriers, just as that under dc hot-carrier stress. The qualitative comparison of the electric field and carrier flow through the junction for the four stress conditions as well as the difference in the degradation mechanism between MOSFETs and poly-Si TFTs are also provided.

New Bidirectional T-Shaped Triple-Gate n-Type Polycrystalline Silicon Thin-Film Transistors Formed by Low-Temperature Sequential Lateral Solidification Process to Reduce of Kink Effects

A new bidirectional T-shaped triple-gate device structure, which suppresses the kink effect of sequential lateral solidification (SLS)-processed polycrystalline silicon thin film transistors (poly-Si TFTs), is proposed and fabricated without any additional process. The proposed poly-Si TFTs have a lateral grain growth in channels, similar to TFTs fabricated by SLS or continuous wave (CW) laser crystallization. The whole current flow of the proposed device is mainly affected by the grain boundaries of lateral grain growth. The bidirectional T-shaped triple-gate structure has incorporated a channel located parallel to the lateral grain growth direction, and the another channel located vertically to the lateral grain growth direction. It is verified from experimental and simulation results that the proposed bidirectional T-shaped triple-gate TFT effectively suppresses the kink current of poly-Si TFT with anisotropic mobility in the triple-gate structure. Our experimental results show that the proposed bidirectional T-shaped triple-gate TFT can suppress the kink effect more effectively than the conventional dual-gate TFT, and L-shaped dual-gate TFT and can improve reliability under the high drain bias condition. The proposed device demonstrates that bidirectional operation is possible for integrated circuits compared with the L-shaped dual-gate structure that shows only fixed one-directional behavior. The proposed device exhibits a very low output conductance in the saturation regime, and this result indicates that higher output resistance is obtained in the proposed bidirectional T-shaped triple-gate TFT.