Abstract
Based on charge conservation assumption, analytical models of the drain-induced grain barrier lowering effect are developed for polysilicon films by 1-D Poisson's equation and for polysilicon thin-film transistors (poly-Si TFTs) by quasi-2-D Poisson's equation. It is shown that the voltage drop at the lower barrier side is less than that at the higher barrier side for both poly-Si films and poly-Si TFTs when applying a lateral bias across the grain-boundary barrier.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
