Dual-Gate Polycrystalline Silicon Thin-Film Transistors with Intermediate Lightly Doped Region

Abstract

I have proposed and developed dual-gate polycrystalline silicon thin-film transistors (poly-Si TFTs) with an intermediate lightly doped region (LDR) for the reduction of leakage current. The proposed poly-Si TFTs are easily fabricated and have a symmetric structure less sensitive to misalignment than the conventional LDD poly-Si TFTs. In the proposed TFTs, it is proved that a decrease in leakage current is due to a reduction in lateral electric field at the drain edge and a reduction in on-current is caused by an increase in the resistance of the LDR. The leakage current of the proposed TFTs is significantly reduced and the maximum ON/OFF current ratio is obtained with a 2 µm LDR length and a 2×1013/cm2 LDR implant dose.