Abstract

Abstract This study investigates how trap charges in the back oxide layer affect the memory performance of 3D NAND flash memory. We used TCAD to simulate the effect on cell reliability, focusing on retention and interference characteristics, based on changes in current paths and program speed as initial cell characteristics. Additionally, we applied these findings to various channel structures — planar, concave, and convex — that can occur in 3D NAND. Our results indicate that the optimal trap charge for enhancing cell performance lies between -10¹¹ and -10¹⁰ /cm³ and should not exceed -1011 /cm3. Through this research, we can expect the potential for effectively inserting trap charges in actual manufacturing processes to improve the performance characteristics of 3D NAND cells.

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.