P-channel JFET Research Articles

CJFET Differential Pairs’ Constructions and Characteristics for Design of Cbicjfet Differential Amplifiers and Differential Difference Amplifiers’

We have developed technology and construction solutions system to increase differential pairs (DP) of JFet with p- and n-channels identity, which are included into silicon complementary bipolar process of SPE “Pulsar” (Moscow). The possibility of creating several types of JFet DPs within the process is shown. The paper presents the results of experimental studies of two types of DP JFet designs with p- and n-channels for the spread of gate-source voltage ΔVGS depending on the drain current and drain-source voltage. The main features of the first design of p-channel JFets were the following: formation of drain/source area due to passive base of npn-transistor and deep collector areas for pnp-transistor; channel formation based on p-layer collector of pnp-transistor; formation of bottom gate using p+ buried layer; top gate formation due to active base and polysilicon emitter of npn-transistor. A feature of the second JFet design was top gate formation due to passive base. The designs of the first and second types of n-channel Jfet were formed similarly, taking into account the replacement of the applied areas of bipolar transistors with opposite ones in the type of conductivity. It was found that with increasing drain current ΔVGS decreases, and with increasing drain-source voltage ΔVGS at high currents increases for DP based on p-channel JFet with the first type of design. The maximum difference ΔVGS was in the range of 5–80 mV for a given differential pair JFet with a p-channel. On plots for DP p-channel JFet with the second type design a significantly lower voltage spread ΔVGS was shown: for example, for the drain current ID = 50 μA the voltage spread ΔVGS did not exceed 10 mV. In this case the voltage spread ΔVGS practially did not depend on drain-source voltage in contrast to differenctial pair of the first type. The second type JFet n-channel differential pairs like for the DP p-channel JFet provided lower spread values in comparison with the first type design: ΔVGS reached values of 5-20 mV. Moreover, for the design of the second type, a significantly weaker effect of the drain-source voltage on ΔVGS was observed at high current densities. The developed designs of differential pairs based on p- and n-channel JFet are recommended for use in organizing the production of CBiCJFet analog circuits, including operations at low temperatures.

Modeling of porous silicon junction field effect transistor gas sensors: Insight into NO2 interaction

In this paper a lumped parameter electrical model for porous silicon junction field effect transistor (PSJFET) gas sensors is presented and experimentally validated. The PSJFET is an integrated p-channel JFET device modified with a porous silicon layer, the latter acting as sensing element. The model is described by using an analytical closed-form expression, which quantitatively links the sensor current to the analyte concentration in the environment, and validated by using experimental data of PSJFETs exposed to both synthetic air and NO2 with concentration of 300 ppb. Best fitting of experimental data with the proposed model allows one to get quantitative information on the effect of NO2 adsorption/desorption at the PS surface on electrical PS parameters, such as its conductance and surface charge density.

Complementary logic with 60 nm poly gate JFET for 0.5 V operation

Digital logic based on nanoscale complementary junction field effect transistors in silicon is reported in order to address scaling issues with CMOS. For the first time, complementary logic based on an enhancement mode JFET (cJFET), consisting of n- and p-channel JFET transistors built on bulk silicon and SOI with 60 nm gate length operating at 0.5 V has been demonstrated. Scalability of this technology has been confirmed by simulation of JFET devices with channel length equal to 16 nm.

A novel power-controlling approach for integrated, conductometric gas sensors

An original power controlling driving/reading circuit for Porous Silicon JFET (PSJFET) gas sensors is presented. The PSJFET is an integrated p-channel JFET with two independent gates: a meso-structured PS layer, acting as a sensing, floating gate, which modulates the JFET current upon adsorption/desorption of specific analytes, and a high-impedance electric gate, which allows the JFET current tuning independently from analytes in the environment. The circuit exploits the independence of the sensing and electrical gate terminals to set/control the sensor power-dissipation, which is kept almost constant independently from adsorption/desorption-induced effects, while simultaneously carrying out a current-voltage conversion. For such a purpose, a negative feedback loop is used to modulate the PSJFET electric gate voltage, which becomes the output signal, while keeping constant the source-drain sensor current and, hence, the power dissipation. The proposed approach is validated by performing time-resolved measurements on PSJFET sensors under different NO2 concentrations (100ppb, 300ppb, 500ppb), at room temperature.

Spectroscopic and imaging performance of DEPFET pixel sensors

DEPFET pixel sensors consist of a p-channel JFET directly integrated into a high-ohmic n-silicon substrate. They offer a very low-noise performance at room temperature and are therefore of interest for applications in biomedicine, X-ray astronomy and particle physics. Measurements on single pixel devices demonstrating the low-noise potential of DEPFET sensors are shown. The DEPFET pixel bioscope system is based on a 64×64 matrix of DEPFET pixels. Measurements of the homogeneity of the charge collection efficiency and of the spatial resolution of the system as well as on the capability of DEPFET sensors to detect tritium with a good efficiency are presented.

Noise degradation induced by /spl gamma/-rays on P- and N-channel junction field-effect transistors

This paper compares the effects of /spl gamma/-rays on the noise behaviour of P- and N-channel JFETs intended as front-end elements in radiation detector preamplifiers. It will be shown that exposure to /spl gamma/-rays affects the noise spectral density in a way which is substantially different for the two types of devices. As a result of the noise analysis it is suggested that in preamplifiers exposed to /spl gamma/-rays the P-channel JFET should be preferred at processing times in the 1-to-10 /spl mu/s range, while the N-channel device remains superior in applications involving processing times below 0.1 /spl mu/s.

Constant-resistance deep-level transient spectroscopy in Si and Ge JFET's

The recently introduced constant-resistance deep-level transient spectroscopy (CR-DLTS) was successfully applied to study virgin and radiation-damaged junction field-effect transistors (JFET's). We have studied three groups of devices: commercially available discrete silicon JFET's; virgin and exposed to high-level neutron radiation silicon JFET's, custom-made by using a monolithic technology; and commercially available discrete germanium p-channel JFET's. CR-DLTS is similar to both the conductance DLTS and to the constant-capacitance variation (CC-DLTS). Unlike the conductance and current DLTS, it is independent of the transistor size and does not require simultaneous measurement of the transconductance or the free-carrier mobility for calculation of the trap concentration. Compared to the CC-DLTS, it measures only the traps inside the gate-controlled part of the space charge region. Comparisons have also been made with the CC-DLTS and standard capacitance DLTS. In addition, possibilities for defect profiling in the channel have been demonstrated. CR-DLTS was found to be a simple, very sensitive, and device area-independent technique which is well suited for measurement of a wide range of deep level concentrations in transistors.

Study of a DEPJFET pixel matrix with continuous clear mechanism

A new kind of silicon pixel detector with integrated amplification has been built and tested. Each pixel consists of a p-channel JFET located on a fully depleted substrate. The pixel size can be customized by using a drift-chamber-like transport mechanism in each pixel. The homogeneity of the signal response of a small matrix was investigated with a laser diode. The measured rise time and gain of the device are analyzed with a simple small signal model.

Novel p-JFET embedded in silicon radiation detectors that avoids preamplifier feedback resistor

The paper describes the design and the performance of an original p-channel JFET embedded in the collecting anode of a silicon radiation detector. The choice of a p-channel transistor, whose gate-to-channel junction is forward biased by the leakage current from the detector, avoids the preamplifier feedback resistor and performs a continuous dc reset of the collected charge. The reported design, fully compatible with the detector fabrication, makes the operation of the detector extremely simple, ensures the best charge collection capability and leads to improved charge resolution. The first detector produced with this type of transistor has a resolution of 27 electrons rms in the measurement of the collected charge at room temperature for a pixel active area of about 0.1 mm/sup 2/, and of 22 electrons rms at T=210 K. >

Design of a high-performance, low-noise charge preamplifier

A high-performance, low-noise charge preamplifier integrated circuit is designed and tested for the Superconducting Super Collider. The amplifier is fabricated in a new dielectrically isolated (DI), radiation-hardened, very-high-frequency (VHF) BIFET IC process technology from Harris Corporation. This new process provides n-p-n, p-n-p, and p-channel JFET devices which are both radiation-hardened, tested to 3 Mrad of total gamma ray exposure and 3*10/sup 14//cm/sup 2/ neutron dosage, and provides high-frequency performance. The new charge preamplifier provides improved performance with an output rise time of 65 ns, input inferred noise of 28.6 mu V, or 3575 electrons, and power dissipation less than 33.7 mW. The circuit design is discussed with attention given to those design characteristics needed to specifically accommodate low noise with the new radiation-hardened process.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

JFET-PMOS technology, in the design of monolithic preamplifier systems for multielectrode detectors

Some basic steps in the development of a low-noise monolithic preamplifier system for multielectrode detectors are reviewed. Some of these steps refer to the realization of an effective filter on the monolithic chip. Others were oriented toward arriving at a technology suitable for a low-noise design. A nonhomogeneous monolithic process combining N- and P-channel JFET and N- and P-channel MOS on the same substrate meets the objective. Radiation hardening considerations restricted the design to two device categories only, NJFET and PMOS. As a preliminary result of the effort in the areas of filter design and technology development, a 64-channel preamplifier system for microstrip detectors is described. >

Investigations of an Antimony Doped Poly-Silicon Gate Structure for P-Type JFET Applications

AbstractA polysilicon gate structure for application as gate material in p-channel JFET's is presented. The structure was manufactured using solid-phase epitaxy of an evaporated antimony/amorphous—silicon layer. The fabrication process together with experimental evaluation of both diode and JFET characteristics is given. The structure shows near ideal n+p-junction behaviour and the fabricated JFET's are normally off with good values of subthreshold swing and transconductance.

A monolithic p-channel JFET quad op amp with in-package trim and enhanced gain-bandwidth product

An amplifier that uses an analog resistive trim element (trimistor) that can be reduced in value by Al/Si filaments formed by an alloying process is described. Filament generation and their lengths are controlled by current pulses through the element. A general in-package trim technique was developed using the trimistor and a high-voltage high-current diode, allowing the package pins to be multifunctional. This combination permits the input offset voltage for each channel of a quad op amp to be trimmed in the package to 10 /spl mu/V. The differential input stage utilizes JFET followers, which allows the separation of JFET/bipolar biasing currents. This results in a low offset voltage temperature coefficient (1/spl sigma/) of 2.5 /spl mu/V//spl deg/C. The gain-bandwidth product is enhanced over the unity-gain frequency by using a dual-doublet frequency-compensation technique. One doublet is defined using the JFET follower with feedforward capacitance, and the second doublet is formed by local positive AC feedback applied to the input current mirror. The amplifier is unity-gain stable, with a 100 MHz gain-bandwidth product (at 100 kHz) and 25 V//spl mu/S slew rate. The symmetrical quad layout is 80/spl times/120 mil/SUP 2/ with 6% of the area dedicated to trim. The die is suitable for a 14-pin narrow-body surface-mount package.

Design techniques for improving the HF response of a monolithic JFET operational amplifier

Bandwidth limitations of an operational amplifier are explored in relation to the second-order frequency response caused by the output follower's inductive emitter impedance when driving capacitive loads or by the local AC feedback associated with the Miller integration function. The substrate p-n-p follower is shown to seriously degrade the bandwidth in the sink mode due to its low /spl omega//SUB /spl tau//. New design techniques are discussed which use the integration capacitor to provide local AC feedback around a new all-n-p-n transistor output stage. This reduces both the open-loop distortion and the quiescent output resistance for a given quiescent current. This also maximizes the lower limit of the inductive frequency range in the sink mode to improve the second-order frequency responses when driving capacitive loads. The multipole local AC feedback loop (Miller loop) is analyzed, and a method of compensation is described which uses pole splitting and feedforward techniques within the Miller loop. As a result, a general-purpose monolithic p-channel JFET quad operational amplifier has been fabricated with standard low-cost technology; the amplifier achieves a 10-MHz bandwidth and a 45-V//spl mu/s slew rate, while consuming only 2.1 mA/amplifier.

A new bipolar process-borsenic

A novel bipolar process, with arsenic emitters, has been developed. The base and the emitter are simultaneously diffused from an oxide source containing B/SUB 2/O/SUB 3/ and As/SUB 2/O/SUB 3/. Because of the slow diffusion of B in the presence of As, extremely shallow junctions have been obtained. n-p-n transistors with high h/SUB FE/, high breakdown, high f/SUB T/, and very little low current h/SUB FE/ falloff have been fabricated. Lateral p-n-p and p-channel JFET's have also been fabricated on the same chip without any extra processing step.