Nonuniform Channel Doping Research Articles

Achievement of extremely small subthreshold swing in Vertical Source-All-Around-TFET with suppressed ambipolar conduction

In this manuscript, we come up with a new line-tunneling-based channel-engineered GaAsSb/GaSb heterojunction Source-All-Around Vertical Nanowire TFET (SAA-NW-VTFET) and analyzed by Sentaurus TCAD-3D simulation. In this proposed model, increased tunneling area at the source-channel interface and the n+-pocket region, along with selective III-V compound semiconductors, have boosted the ON-current in the device. On the other hand, non-uniform channel doping and reduced tunneling area at the drain end have significantly suppressed the ambipolar current. The significant results in terms of ON-current (ION = 0.789 × 10−4 A/μm), OFF-current (IOFF = 1.08 × 10−17 A/μm), ION/IOFF ratio (7.25 × 1012), threshold voltage (0.2 V), point subthreshold swing (SS = 3 mV/dec) and average SS (SSavg = 7 mV/dec) are obtained in the simulation study. In addition, the effect of temperature (250 K–450 K) on device DC characteristics and DIBT is also presented.

A Steady-State LDMOST Model Based on Semi-Numerical Regional Approach

This paper presents a high-voltage lateral DMOS transistor (LDMOST) model for steady-state condition.The device modelling method is basically based on a semi-numerical regional approach.The complete model is physical, so that it accounts for unique LDMOST features such as non-uniform channel doping, non-planar drift region and space-charge-limited current flowing.Themodelcalculationsshow good overall agreement withthe measured results.This DMOS transistor model, whichcan beapplicable to a SPICE-like circuit simulator, might be useful in technology CAD of high-voltage power ICs.

Parameter Extraction for the PSPHV LDMOS Transistor Model

This paper details a robust parameter extraction flow for the PSPHV LDMOS transistor model. The procedure uses a global scaling parameter set and accounts for self-heating. We describe how to determine parameters associated with important physical effects specific to PSPHV: non-uniform lateral channel doping; the Kirk effect; internal drain voltage clamping; and the drain expansion effect. The method is verified on devices from different technologies. Verilog-A code for PSPHV is publicly available.

Analysis and Modeling of Temperature and Bias Dependence of Current Mismatch in Halo-Implanted MOSFETs

We present an analytical model that accurately captures anomalous matching characteristics of drain current in a halo-implanted MOSFET across bias, geometry, and temperature. It is shown that the variation in drain current in different gate bias regimes results from the random-dopant fluctuations (RDFs) in different spatial regions across the channel of the device with nonuniform channel doping. Such effects cannot be captured by existing compact models. Using the impedance field method to calculate the relative contributions of the RDF in the higher doped halo region and the lower doped channel region, we demonstrate, for the first time, an analytical model that can successfully capture the drain current mismatch from subthreshold to strong inversion. We also report for the first time the unique temperature dependence of matching of the drain current in halo-implanted devices and propose a model to capture this behavior. The model is validated using extensive technology computer-aided design analysis and experimental data and is can be extended to the framework of the industry standard BSIM-BULK (formerly BSIM6) MOS model.

Total Ionizing Dose Response of Different Length Devices in 0.13 μm Partially Depleted Silicon-on-Insulator Technology**Supported by the Weapon Equipment Pre-Research Foundation of China under Grant No 9140A11020114ZK34147, and the Shanghai Municipal Natural Science Foundation under Grant Nos 15ZR1447100 and 15ZR1447200.

An anomalous total dose effect that the long length device is more susceptible to total ionizing dose than the short one is observed with the partially depleted silicon-on-insulator technology. The measured results and 3D technology computer aided design simulations demonstrate that the devices with different channel lengths may exhibit an enhanced reverse short channel effect after radiation. It is ascribed to that the halo or pocket implants introduced in processes results in non-uniform channel doping profiles along the device length and trapped charges in the shallow trench isolation regions.

Role of non-uniform channel doping in improving the nanoscale JL DG MOSFET reliability against the self-heating effects

In this paper, a new hybrid approach by combining numerical investigation and Support Vector Machines (SVMs) classifier is proposed to study the thermoelectric performance of nanoscale Double Gate Junctionless DG JL MOSFET. In this context, a new Figure of Merit (FoM) parameter which combines both electrical and reliability characteristics is proposed. Moreover, the impact of Gaussian channel doping profile (GCD) in enhancing the DG JL MOSFET reliability against the self-heating effects (SHEs) is presented. The proposed design thermal stability and electrical characteristics are investigated and compared with those of the conventional structure in order to reveal the device performance including SHEs. It is found that the amended channel doping has a profound implication in improving both the device electrical performance and the reliability against the undesired self-heating and short channel effects (SCEs). Furthermore, the transistor thermal behavior analysis involves classification of the device performance by taking into account the device reliability. For this purpose, SVMs are adopted for supervised classification in order to identify the most favorable design configurations associated with suppressed SHEs and improved electrical performance. We find that the proposed design methodology has succeeded in selecting the better designs that offer superior reliability against the SHEs. The obtained results suggest the possibility for bridging the gap between high electrical performances with better immunity to the SHEs.

Effects of non-uniform doping on junctionless transistor

In this paper, we study the effects of non-uniform channel doping on junctionless transistor (JLT) using 3D quantum simulations. The JLT devices require a uniformly doped ultrathin channel. Although we take uniform doping for study, in practice, it will be technologically difficult to obtain. For technological reason, after thermal annealing, the impurity profile in semiconductor device becomes uniform along lateral channel direction and non-uniform along vertical direction. Here, we show that this directly affects the short channel behaviour and reduces on-current.

Evolution of Unified-RAM: 1T-DRAM and BE-SONOS Built on a Highly Scaled Vertical Channel

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Geometry, Temperature, and Body Bias Dependence of Statistical Variability in 20-nm Bulk CMOS Technology: A Comprehensive Simulation Analysis

Conventional bulk CMOS, which is arguably most vulnerable to statistical variability (SV), is the workhorse of the electronic industry for more than three decades. In this paper, the dependence of the SV of key figures of merit on gate geometry, temperature, and body bias in 25-nm gate-length MOSFETs, representative for the 20-nm CMOS technology generation, is systematically investigated using 3-D statistical simulations. The impact of all relevant sources of SV is taken into account. The geometry dependence of the threshold-voltage dispersion (and indeed the dispersion of other key transistor figures of merit) does not necessarily follow the Pelgrom's law due to the complex nonuniform channel doping and the interplay of different SV sources. The DIBL variation, for example, follows a log-normal distribution. The temperature significantly affects the magnitudes of threshold voltage, subthreshold slope, ON/OFF currents, and the corresponding statistical distributions. Reverse body bias increases the threshold voltage and its fluctuation, while forward body bias reduces both of them.

Planar junctionless transistor with non-uniform channel doping

We propose a planar junctionless transistor (JLT) in silicon-on-insulator (SOI) with non-uniform channel doping in vertical direction to improve the ON to OFF drain current ratio. In single gate JLT in SOI, a thin device layer is depleted in the off-state from the top of the layer and the leakage current flows through bottom of the device layer, and the leakage current depends on the device layer thickness. We show that the decrease of doping in vertical direction suppresses the leakage current flowing through the bottom of the device by decreasing conductivity at the bottom of the device layer.

THE IMPACT OF CHANNEL ENGINEERING ON SHORT CHANNEL BEHAVIOR OF NANO FIN-FETs

This short note presents the simulation result on the effect of channel engineering i.e., non-uniform channel doping on short channel effects (SCE) in nano Fin-FET devices using Silvaco TCAD tool. The nano Fin-FET structures were generated using DEVEDIT and the effect of channel doping concentration has been studied. The optimum doping concentration profile has been observed to considerably improve the SCE in general and drain induced barrier lowering (DIBL) in particular.

Nonuniform threshold voltage profile in a-Si:H thin film transistor stressed under both gate and drain biases

In this paper we show that an a-Si:H thin film transistor (TFT) stressed with bias temperature stress (BTS) under both gate bias and drain bias produces a nonuniform threshold voltage profile which can be obtained from the quasi-Fermi potential profile and the threshold voltage (Vt)-shift data of BTS under the gate bias only. The transfer and output characteristics calculated with this nonuniform Vt-profile agreed well with the measured data, where the calculation was performed using both the gradual-channel approximation and independently the AIM Spice simulation with its level-15 a-Si TFT model. It is shown that local threshold voltage is high at the source and decreases toward the drain. Due to the nonuniform Vt-profile in the channel, the drain current level is higher in the forward direction, where the source and drain electrodes are the same between measurement and BTS, than in the reverse direction, where source and drain electrodes are interchanged. The forward and reverse I-V characteristics are somewhat similar to those of metal-oxide-semiconductor field-effect transistors with nonuniform channel doping.

Series Resistance and Mobility Extraction Method in Nanoscale MOSFETs

This paper presents a BSIM-based method for source/drain series resistance and mobility extraction in nanoscale strained-silicon metal oxide semiconductor field effect transistors (MOSFETs) with halo implants. This method is more accurate than the conventional channel-resistance and shift and ratio method because it considers the gate-length dependence of mobility caused by local uniaxial stress and laterally nonuniform channel doping. We have verified this method using samples with different stressor/doping conditions and good agreement with experimental data has been obtained. The accuracy of the Berkeley Short-channel IGFET model (BSIM) extraction method is also proven by simulated current–voltage characteristics with different external resistant values. Significant mobility degradation in the short-channel regime has been observed for various uniaxial stressors. This method may serve as a suitable process monitor tool for ultrashallow junction and strained process development.

Improved generation lifetime model for the electrical characterization of single- and double-gate SOI nMOSFETs

This work proposes a refined technique for the extraction of the generation lifetime in single- and double-gate partially depleted SOI nMOSFETs. The model presented in this paper, based on the drain current switch-off transients, takes into account the influence of the laterally non-uniform channel doping, caused by the presence of the halo implanted region, and the amount of charge controlled by the drain and source junctions on the floating body effect when the channel length is reduced. The obtained results for single-gate (SG) devices are compared with two-dimensional numerical simulations and experimental data, extracted for devices fabricated in a 0.1 µm SOI CMOS technology, showing excellent agreement. The improved model to determine the generation lifetime in double-gate (DG) devices beyond the considerations previously presented also consider the influence of the silicon layer thickness on the drain current transient. The extracted data through the improved model for DG devices were compared with measurements and two-dimensional numerical simulations of the SG devices also presenting a good adjustment with the channel length reduction and the same tendency with the silicon layer thickness variation.

A new method to simulate random dopant induced threshold voltage fluctuations in sub-50 nm MOSFET’s with non-uniform channel doping

In this paper, based on a precise and efficient analytical function of relatively realistic dopant fluctuations, a new method is proposed to simulate the threshold voltage variation of MOSFET’s with non-uniform channel doping due to random dopant fluctuations. Both the number and position fluctuations of dopants are taken into account. Using this method, 2500 microscopically different devices under certain process conditions that cover the range of channel length L from 35nm to 90nm, oxide thickness Tox from 1nm to 4nm and channel surface doping concentration NA from 1×1018 to 5×1018cm−3 are simulated to show how our method works.

New fundamental insights into capacitance modeling of laterally nonuniform MOS devices

In compact transistor modeling for circuit simulation, the capacitances of conventional MOS devices are commonly determined as the derivatives of terminal charges, which in their turn are obtained from the so-called Ward-Dutton charge partitioning scheme. For devices with a laterally nonuniform channel doping profile, however, it is shown in this paper that no terminal charges exist from which the capacitances can be derived. Instead, for such devices, a new model is presented for the capacitances themselves. Furthermore, a method is given to incorporate such a capacitance model into circuit simulators, which are traditionally based on terminal charge models. Comparison with two-dimensional device simulations and a segmentation model shows that for a constant mobility, the new capacitance model provides an accurate description for a MOSFET with a laterally diffused channel doping profile. Through a comparison with high-frequency measurements, the agreement between model and experimental results is discussed.

Scaling characteristics of fNQS and ft in NMOSFETs with uniform and non-uniform channel doping

Extensive process and device simulations are performed to investigate the non-quasi-static transition frequency (fNQS ) and unity gain frequency (ft ) behaviour of the NMOSFETs at different technology nodes, varying from 0.5 µm to 90 nm. The scaled transistors are constrained to have identical leakage current (IOFF ) at scaled voltages to facilitate a fair comparison. fNQS exhibits a turn-around in the 100 nm regime irrespective of the channel engineering. We attribute this effect to the reduced gate over-drive (VGS-Vt ) and lower mobility; which inturn degrades the transconductance (gm ). ft also shows a similar trend. The turn around effect of fNQS and ft disappears, when IOFF constraint is relaxed or the gate over-drive is increased.

Achieving accuracy in modeling the temperature coefficient of threshold voltage in MOS transistors with uniform and horizontally nonuniform channel doping

A thorough investigation on the threshold voltage temperature coefficient (TVTC) in MOS transistors is carried out. The TVTC behavior is analyzed in both conventional MOSFETs with uniformly-doped channel (UDC) and double-diffused devices (DMOS). First, a survey of analytical TVTC models proposed in literature for UDC MOSFETs is presented. Due to the need of simple TVTC expressions also for power devices, the listed UDC models are extended to the DMOS case via the straightforward “maximum doping” approach, which is commonly believed to correctly describe the turn-on mechanism in nonuniformly doped channels (NUDC). The accuracy degree of all TVTC expressions and the adequacy of the above method are—for the first time—deeply analyzed through ATLAS 2-D simulations of both DMOS and ideal UDC structures. As a main result, the “maximum doping” approach is demonstrated too coarse for suitably modeling the underlying DMOS physics. Nevertheless, it is shown that the TVTC in DMOSTs characterized by proper technological parameters is described with reasonable agreement by the Klaassen–Hes UDC model. Conversely, more compact formulations are proved to suffer from an unacceptable inaccuracy regardless of the MOS typology.

Enhancement of device performance in vertical sub-100 nm MOS devices due to local channel doping

For future devices in metal oxide semiconductor technology there is a great interest in down scaling of device dimensions to improve device performance and to increase packing density. New device designs with nonuniform channel doping profiles are investigated to further enhance performance over conventional device designs and to suppress short channel effects. In this work we report sub-100 nm MOS devices with channel delta doping profiles grown using molecular beam epitaxy. Electrical characteristics and carrier transport in these devices are investigated and show significant improvements compared to conventional devices. Sharp channel profiles facilitate control of electric field and this “field engineering” improve the breakdown characteristics and provide better control of threshold voltage.

Numerical simulation of implanted top-gate 6H–SiC JFET characteristics

A detailed numerical analysis of implanted top-gate 6H–SiC JFET structures was performed revealing the influence of a non-uniform channel doping profile. Based on structural parameters extracted from simulations of the device characteristics at various bias conditions and temperatures, we obtain channel mobility parameters close to Hall data for bulk epitaxial layers.