Abstract

In this manuscript, we come up with a new line-tunneling-based channel-engineered GaAsSb/GaSb heterojunction Source-All-Around Vertical Nanowire TFET (SAA-NW-VTFET) and analyzed by Sentaurus TCAD-3D simulation. In this proposed model, increased tunneling area at the source-channel interface and the n+-pocket region, along with selective III-V compound semiconductors, have boosted the ON-current in the device. On the other hand, non-uniform channel doping and reduced tunneling area at the drain end have significantly suppressed the ambipolar current. The significant results in terms of ON-current (ION = 0.789 × 10−4 A/μm), OFF-current (IOFF = 1.08 × 10−17 A/μm), ION/IOFF ratio (7.25 × 1012), threshold voltage (0.2 V), point subthreshold swing (SS = 3 mV/dec) and average SS (SSavg = 7 mV/dec) are obtained in the simulation study. In addition, the effect of temperature (250 K–450 K) on device DC characteristics and DIBT is also presented.

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