Parameter Extraction for the PSPHV LDMOS Transistor Model

Kejun Xia,Colin C Mcandrew,Ronald Van Langevelde

doi:10.1109/jeds.2020.3011635

Kejun Xia, Colin C Mcandrew + Show 1 more

Open Access

https://doi.org/10.1109/jeds.2020.3011635

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Abstract

This paper details a robust parameter extraction flow for the PSPHV LDMOS transistor model. The procedure uses a global scaling parameter set and accounts for self-heating. We describe how to determine parameters associated with important physical effects specific to PSPHV: non-uniform lateral channel doping; the Kirk effect; internal drain voltage clamping; and the drain expansion effect. The method is verified on devices from different technologies. Verilog-A code for PSPHV is publicly available.

Highlights

Laterally diffused MOS (LDMOS) transistors are widely used in integrated circuits (ICs) for applications such as switch-mode power supplies, power amplifiers, power management, and motor drivers
PSPHV consists of an enhanced version of the PSP103.6 MOS transistor model [2] for the intrinsic channel, a modified version of the JFETIDG dual-gate JFET model [3] for the drift region, and JUNCAP2 [4], extended to improve modeling at high forward bias, for parasitic junction diodes
The parameter extraction process for PSPHV is reasonably complex because LDMOS transistors are complex devices, PSPHV is a fairly complex model

Summary

INTRODUCTION

Diffused MOS (LDMOS) transistors are widely used in integrated circuits (ICs) for applications such as switch-mode power supplies, power amplifiers, power management, and motor drivers. We developed an accurate surface-potential based compact LDMOS transistor model PSPHV [1] to help design and optimize such ICs. PSPHV consists of an enhanced version of the PSP103.6 MOS transistor model [2] for the intrinsic channel, a modified version of the JFETIDG dual-gate JFET model [3] for the drift region, and JUNCAP2 [4], extended to improve modeling at high forward bias, for parasitic junction diodes. PSPHV consists of an enhanced version of the PSP103.6 MOS transistor model [2] for the intrinsic channel, a modified version of the JFETIDG dual-gate JFET model [3] for the drift region, and JUNCAP2 [4], extended to improve modeling at high forward bias, for parasitic junction diodes These components are integrated into a single Verilog-A code which is publicly available [5]. Our procedure recognizes this fact: below “extract” means either an initial manual tuning, or small optimization, of one or a small number of parameters to fit a limited set of data, and “optimization” means the step is more substantial, and not manual, and involves adjusting multiple parameters to fit multiple data sets, often over geometry and temperature as well as over bias

OVERVIEW AND GLOBAL SWITCHES

CONCLUSION