Negative Drain-induced Barrier Lowering Research Articles

Performance improvements in complementary metal oxide semiconductor devices and circuits based on fin field-effect transistors using 3-nm ferroelectric Hf0.5Zr0.5O2

In this work, a conventional HfO2 gate dielectric layer is replaced with a 3-nm ferroelectric (Fe) HZO layer in the gate stacks of advanced fin field-effect transistors (FinFETs). Fe-induced characteristics, e.g., negative drain induced barrier lowering (N-DIBL) and negative differential resistance (NDR), are clearly observed for both p- and n-type HZO-based FinFETs. These characteristics are attributed to the enhanced ferroelectricity of the 3-nm hafnium zirconium oxide (HZO) film, caused by Al doping from the TiAlC capping layer. This mechanism is verified for capacitors with structures similar to the FinFETs. Owing to the enhanced ferroelectricity and N-DIBL phenomenon, the drain current (IDS) of the HZO-FinFETs is greater than that of HfO2-FinFETs and obtained at a lower operating voltage. Accordingly, circuits based on HZO-FinFET achieve higher performance than those based on HfO2-FinFET at a low voltage drain (VDD), which indicates the application feasibility of the HZO-FinFETs in the ultra-low power integrated circuits.Graphical abstract

Unveiling the mechanism behind the negative capacitance effect in Hf0.5Zr0.5O2-Based ferroelectric gate stacks and introducing a Circuit-Compatible hybrid compact model for Leakage-Aware NCFETs

This paper addresses the lack of understanding of the origin of negative capacitance (NC) effect in the hafnium zirconium oxide (HZO) ferroelectric (FE) gate stack and proposes a new circuit-compatible hybrid compact model for NC field-effect transistors (NCFETs). The model supports Landau and Preisach FE models, encompassing multiple FE domains, FE leakage, and FE damping. The proposed model is experimentally validated, and the intrinsic switching speed of HZO is predicted. It is revealed that the NC effect in HZO stems from a mismatch in free charge and polarization switching rates. Performance evaluation of the model reveals that HZO-NCFET achieves ∼1.18x and ∼9.17x higher amplification at low and high frequencies compared to its PZT-NCFET counterpart. Our study demonstrates the superior ON-current (2.74 mA/µm) of the Engineered Leaky-HZO NCFET, surpassing FinFET and Germanium-source L-shaped TFET by ∼7.89x and ∼4.81x, respectively. This study briefly examines the direct causes of the negative drain-induced barrier lowering effect and negative differential resistance effect in Landau NCFETs. Furthermore, we emphasize the crucial role of FE thickness in determining the magnitude of the NC effect, offering valuable insights for the design and optimization of NC-based devices and circuits. Analysis of the Miller effect in NCFET-based inverters demonstrates significant improvements owing to high ON-current and voltage amplification, making them suitable for high-speed NCFET-based circuitry. Landau and Preisach NCFET-based inverters exhibit (50.70%, 51.34%) lower overshoots and (28.45%, 28.61%) reduced propagation delay compared to the NC nanowire FET-based inverter. Moreover, NCFET-based 2:1 fork circuits significantly reduce (46.69%, 51.37%) critical clock skew compared to CMOS FET-based circuits, showcasing the potential of NCFET technology in addressing timing violations in random logic paths. Furthermore, the Landau and Preisach NCFET-based ring oscillators (ROs) achieve (39.97%, 49.38%) and (52.65%, 62.92%) higher oscillation frequencies (fOSC) compared to state-of-the-art graphene FET-RO and CMOS-RO, respectively. The 15-stage Leaky-HZO and Engineered Leaky-HZO NCFET-ROs outperform the double gate-FET-RO by ∼2.19x and ∼16.69x in terms of fOSC, highlighting their superior performance in frequency-domain metrics. These findings demonstrate the potential of NCFET-based digital and mixed-signal circuits for high-performance integrated circuit designs.

Analysis of Drain-Induced Barrier Lowering for Gate-All-Around FET with Ferroelectric

This study presents an analytical model for the drain-induced barrier lowering (DIBL) of a junctionless gate-all-around FET with ferroelectric, utilizing a 2D potential model. A multilayer structure of metal-ferroelectric-metal-insulator-semiconductor is used as the gate, as well as the remanent polarization and coercive field values corresponding to HZO are used. The DIBLs obtained with the proposed model demonstrate good agreement with those obtained using the second derivative method, which relies on the 2D relationship between drain current and gate voltage. The results demonstrate that an increase in ferroelectric thickness leads to a negative DIBL value due to the ferroelectric charge. Additionally, there exists an inverse relationship between ferroelectric thickness and channel length to achieve a DIBL value of 0. This condition is satisfied only with the increase of the ferroelectric thickness as the channel radius and insulator thickness increase. The DIBLs increase with higher remanent polarization and lower coercive field, remaining constant when the ratio of remanent polarization and coercive field is maintained.

Negative Capacitance Field Effect Transistors based on Van der Waals 2D Materials.

Steep subthreshold swing (SS) is a decisive index for low energy consumption devices. However, the SS of conventional field effect transistors (FETs) has suffered from Boltzmann Tyranny, which limits the scaling of SS to sub-60mVdec-1 at room temperature. Ferroelectric gate stack with negative capacitance (NC) is proved to reduce the SS effectively by the amplification of the gate voltage. With the application of 2D ferroelectric materials, the NC FETs can be further improved in performance and downscaled to a smaller dimension as well. This review introduces some related concepts for in-depth understanding of NC FETs, including the NC, internal gate voltage, SS, negative drain-induced barrier lowering, negative differential resistance, single-domain state,and multi-domain state. Meanwhile, this work summarizes the recent advances of the 2D NC FETs. Moreover, the electrical characteristics of some high-performance NC FETs are expressed as well. The factors which affect the performance of the 2D NC FETs are also presented in this paper. Finally, this work gives a brief summary and outlook for the 2D NC FETs.

Analytical modeling of architecture dependent atypical scaling trends in metal–Hf0.5Zr0.5O2–metal-SiO2–Si negative capacitance transistors

In order to better understand the possible improvement through the incorporation of a ferroelectric (FE) layer in the gate stack of the nanoscale transistor, this work develops analytical expressions to assess the scalability of cylindrical (CYL) nanowire and planar double gate (DG) metal–FE–metal–insulator–semiconductor (MFMIS) negative capacitance (NC) transistors. While predicting a sub-60 mV dec−1 subthreshold swing and a negative drain induced barrier lowering (DIBL), the results indicate that at lower FE thickness, the performance of the NC field effect transistor (NCFET) is primarily governed by the electrostatic integrity of the baseline transistor, i.e. the CYL architecture outperforms planar DG NCFET. However, for relatively thicker T FE, the performance of an MFMIS NCFET is strongly governed by the FE coupling, which indicates the comparable performance of DG and CYL MFMIS NCFETs. The formalism, while predicting atypical trends, showcases a pragmatic design criterion for achieving a sub-60 mV dec−1 subthreshold swing and DIBL-free characteristics in MFMIS NC transistors.

Optimization of Subthreshold Swing and Hysteresis in Hf0.5Zr0.5O2-Based MoS2 Negative Capacitance Field-Effect Transistors by Modulating Capacitance Matching.

Negative capacitance field effect transistors made of Hf0.5Zr0.5O2 (HZO) are one of the most promising candidates for low-power-density devices because of the extremely steep subthreshold swing and high open-state currents resulting from the addition of ferroelectric materials in the gate dielectric layer. In this paper, HZO thin films were prepared by magnetron sputtering combined with rapid thermal annealing. Their ferroelectric properties were adjusted by changing the annealing temperature and the thickness of HZO. Two-dimensional MoS2 back-gate negative capacitance field-effect transistors (NCFETs) based on HZO were prepared as well. Different annealing temperatures, thicknesses of HZO thin films, and Al2O3 thicknesses were studied to achieve optimal capacitance matching, aiming to reduce both the subthreshold swing of the transistor and the hysteresis of the NCFET. The NCFET exhibits a minimum subthreshold swing as low as 27.9 mV/decade, negligible hysteresis (∼20 mV), and the ION/IOFF of up to 1.58 × 107. Moreover, a negative drain-induced barrier lowering effect and a negative differential resistance effect have been observed. This steep-slope transistor is compatible with standard CMOS manufacturing processes and attractive for 2D logic and sensor applications as well as future energy-efficient nanoelectronic devices with scaled power supplies.

Negative capacitance silicon nanotube FET: a subthreshold modeling exploration of sub-60 mV/decade swing, negative drain-induced barrier lowering, and threshold voltage roll-off

Negative capacitance silicon nanotube FET: a subthreshold modeling exploration of sub-60 mV/decade swing, negative drain-induced barrier lowering, and threshold voltage roll-off

Analysis of drain induced barrier lowering for junctionless double gate MOSFET using ferroelectric negative capacitance effect

<abstract> <p>We analyze the drain induced barrier lowering (DIBL) of a negative capacitance (NC) FET using a gate structure such as a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) for a junctionless double gate (JLDG) FET. NC FETs show negative DIBL characteristics according to the ferroelectric thickness. To elucidate the cause of such negative DIBL, the DIBLs are obtained by the second derivative method using the 2D potential distribution and drain current-gate voltage curve. The analytical DIBL model is also presented for easy observation of the DIBL of NC FET. It has been found that the results of this analytical DIBL model are very similar to those of the second derivative method. The results of this analytical DIBL model are also in good agreement with the results of TCAD. As a result, it was found that the negative DIBL phenomenon is caused by the change according to the drain voltage of the charge existing in the ferroelectric material. The negative DIBL phenomenon easily occurred as the ferroelectric thickness increased and the thickness of SiO<sub>2</sub> used as an insulator decreases.</p> </abstract>

Negative drain-induced barrier lowering and negative differential resistance effects in negative-capacitance transistors

In this study, the negative drain-induced barrier lowering (DIBL) and negative differential resistance (NDR) effects are investigated in detail in negative-capacitance field-effect transistors (NCFETs) with a fully depleted silicon-on-insulator structure. We show that the negative DIBL and NDR effects are caused by a decrease in the internal gate voltage, which is closely related to the matching between the ferroelectric capacitance and the total gate capacitance of the underlying FET. Further, we define the remnant-polarization-to-coercive-field ratio (RPE), which can be directly used as a parameter to quantify the DIBL effect and describe the sign of the NDR effect. DIBL tends to be consistent with the same RPE, despite exhibiting different current intensities in the strong inversion region. With regard to different RPE, the DIBL effect decreases but the NDR effect increases as RPE decreases. Our work may provide further insight for NCFET designers to adjust capacitance matching to optimize the DIBL and NDR effects.

Superior Performance of a Negative-capacitance Double-gate Junctionless Field-effect Transistor with Additional Source-drain Doping

In this work, we propose a negative-capacitance double-gate junctionless field-effect transistor (NC-JLFET) with additional source-drain doping for the first time. Superior performance of the NC-JLFET due to source and drain doping concentration is explained in detail. Additionally, the effects of the drain induced barrier lowering (DIBL) and negative differential resistance (NDR) are precisely analyzed in the NC-JLFET. Sentaurus TCAD simulation demonstrates that the additional source-drain-doped NC-JLFET exhibits a higher on/off current ratio ( I ON / I OFF ) and steeper subthreshold swing ( SS < 60 mV/dec) compared to a traditional JLFET. Besides, the negative capacitance effect causes the internal voltage of the gate to be amplified, resulting in negative DIBL and NDR phenomena. Finally, the performance of NC-JLFET can also be optimized by choosing suitable ferroelectric material parameters, such as ferroelectric thickness, coercive field, and remnant polarization. Our simulation study provides theoretical and experimental support for further performance improvement of low-power NCFETs by local structure adjustment.

Analysis and Modeling of Polarization Gradient Effect on Negative Capacitance FET

In this article, we will analyze and provide new insights into the polarization gradient effect of a ferroelectric using TCAD simulation and demonstrate how to model the polarization gradient effect using the negative capacitance FET (NCFET) compact model based on the BSIM framework. A larger value of ${g}$ (the coefficient of polarization gradient effect) results in improved subthreshold slope, smaller OFF-current, smaller drain-induced barrier lowering (DIBL), and smaller output conductance. Inclusion of the polarization gradient effect in the NCFET compact model improves usability because it accurately captures the effects of negative DIBL and negative output conductance.

Effect of Seed Layer on Gate-All-Around Poly-Si Nanowire Negative-Capacitance FETs With MFMIS and MFIS Structures: Planar Capacitors to 3-D FETs

In this article, we successfully fabricated nanowire (NW) negative capacitance (NC)-related ferroelectric FETs (FE-FETs) with two structures: trigate (TG) and gate-all-around (GAA). Planar capacitors with a metal–FE–metal (MFM) structure were investigated first. Post-metal annealing (PMA) at 700 °C resulted in the best ferroelectricity. This condition was considerably different from that of directly stacking onto NWs because of the difference in size and curvature between planar and TG or GAA structures. Because of the addition of an underlying ZrO2 seed layer, Hf $_{{1}- {x}}$ Zr x O2 in the gate-stack has been crystallized before the PMA process. In addition, two different gate-stack configurations, MFM–insulator–semiconductor (MFMIS) and metal–FE–insulator–semiconductor (MFIS), were investigated for the GAA structure. We determined that MFMIS displayed considerably more favorable subthreshold behavior and ON-state current compared with MFIS. NC-related phenomena, such as negative drain-induced barrier lowering and negative differential resistance, were observed.

Effect of Various Geometry Parameters on the Performance of Nanoplate Field Effect Transistor with Negative Capacitance.

In this paper, we investigate the impact of geometry parameters such as ferroelectric layer thickness (TFE), extension length (LExt), overlap length (Lov) on negative capacitance FET (NCFET). The NCFET is designed using HfZrO₂ (HZO) ferroelectric materials and the Nanoplate FET (NPFET) presented as a next generation device. We use the 3-D TCAD Sentaurus simulator to analyze characteristics of the NCFET. The NCFET designed considering the stable condition overcomes the Boltzmann limit (i.e., the physical limit in the S.S., which is 60 mV/decade at 300 K) through the steep subthreshold swing (S.S.) and exhibits negative Drain-induced barrier lowering (DIBL) phenomenon. When examining the characteristics of NPFET and NCFET according to LExt and Lov, the NCFET exhibits gate capacitance (Cgg) tendency opposite to that of the NPFET. The NCFET with the scaled VDD has a significant advantage over the gate delay (τd). The NCFET has better performance in environments where conventional device is more vulnerable to short channel effects (SCEs).

A novel steep slope hybrid InGaZnO TFT with negative DIBL improvement based on the Ag/HfO2 threshold switching device

We present a steep slope hybrid thin film transistor (TFT) that integrates an Ag/HfO2 based threshold switching (TS) with a ferroelectric HfZrO gated InGaZnO TFT. The hybrid TFT shows a minimum subthreshold swing of 16 mV decade. The negative differential resistance effect (NDR) was observed during the switching process of the TS. And the InGaZnO TFT shows a negative drain-induced barrier lowering (DIBL) effect. Furthermore, a Verilog-A model is developed to simulate the hybrid TFT. All of these suggests the as-fabricated hybrid TFT is suitable for low power TFT based applications.

DIBL improvement in hysteresis-free and ferroelectric-gated FinFETs

The improvement of drain-induced barrier lowering (DIBL) in hysteresis-free and ferroelectric-gated fin field effect transistors (FinFETs) [a.k.a., negative capacitance (NC) FinFET] has been experimentally verified. Moreover, all fabricated NC FinFETs (some of which are not hysteresis-free) have successfully shown sub-60-mV/decade subthreshold slope (SS) characteristics. By adjusting both the fin width and channel length, the ferroelectric and dielectric capacitance matching in the gate stacks of FinFETs is successfully implemented, resulting in hysteresis-free NC FinFETs with a 20 mV/decade SS. Finally, the negative DIBL phenomenon in the hysteresis-free NC FinFET has produced an enhanced DIBL of 20.78 mV/V (note that the DIBL of baseline FinFET is 68.89 mV/V at 300 K).

Evaluation of NC-FinFET Based Subsystem-Level Logic Circuits

This paper examines metal–ferroelectric–insulator–semiconductor negative-capacitance FinFET (NC-FinFET) based VLSI subsystem-level logic circuits. For the first time, with the aid of a short-channel NC-FinFET compact model, we confirm the functionality and evaluate the standby-power/switching-energy/delay performance of large logic circuits (e.g., dynamic 4-bit Manchester carry-chain adder and the formal hierarchical 32-bit carry-look-ahead adder) employing 14-nm ultra-low-power NC-FinFETs. Our study indicates that the inverse <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ds</sub> -dependence of threshold voltage ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ), also known as the negative drain-induced barrier lowering, of negative-capacitance field-effect transistor is not only acceptable but also beneficial for the speed performance of both the static and pass-transistor logic (PTL) circuits, especially for the PTL at low <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> .

Experimental observation of zero DIBL in short-channel hysteresis-free ferroelectric-gated FinFET

The experimental investigation for the drain-induced-barrier-lowering (DIBL) in nanometer scale hysteresis-free 100 nm-long ferroelectric-gated FinFET (which employs the voltage-amplifying attribute of Pb(Zr0.52Ti0.48)O3-based ferroelectric capacitor) is done to verify the DIBL improvement. The DIBL of the ferroelectric-gated FinFET (which is evaluated at 10−7 A/μm of drain current) is improved from ∼48 mV/V to ∼32 mV/V. When the DIBL is evaluated at 10−6 A/μm, it is reduced from 22.89 mV/V to ∼0 mV/V. The physical origin of the DIBL enhancement can be understood due to negative DIBL. The negative DIBL effect [a.k.a., drain-induced-barrier-rising (DIBAR)] is originated from a decrease of internal gate voltage, which takes place due to a gate charge reduction with increased drain voltage.

A Closed Form Analytical Model of Back-Gated 2-D Semiconductor Negative Capacitance Field Effect Transistors

Steep slope ( $SS mV/dec at room temperature) negative capacitance (NC) FETs, based on the 2-D transition metal dichalcogenide semiconductor channel materials, may have a promising future in low-power electronics because of their high on-state current and very high on/off ratio. In this paper, we develop an analytically compact drain current model for long-channel back-gated 2-D NC-FETs by solving the classical drift-diffusion equations. The equations describe the transition from depletion to accumulation regimes of operation as a continuous function of gate/drain voltages. The continuity ensures time-efficient simulation of large systems. Several key features of the model are verified by comparing with the experimental data. Specifically, the negative drain induced barrier lowering effect and negative differential resistance effect predicted by the model are successfully observed in our experiments.

Steep-slope hysteresis-free negative capacitance MoS2 transistors.

The so-called Boltzmann tyranny defines the fundamental thermionic limit of the subthreshold slope of a metal-oxide-semiconductor field-effect transistor (MOSFET) at 60 mV dec-1 at room temperature and therefore precludes lowering of the supply voltage and overall power consumption 1,2 . Adding a ferroelectric negative capacitor to the gate stack of a MOSFET may offer a promising solution to bypassing this fundamental barrier 3 . Meanwhile, two-dimensional semiconductors such as atomically thin transition-metal dichalcogenides, due to their low dielectric constant and ease of integration into a junctionless transistor topology, offer enhanced electrostatic control of the channel 4-12 . Here, we combine these two advantages and demonstrate a molybdenum disulfide (MoS2) two-dimensional steep-slope transistor with a ferroelectric hafnium zirconium oxide layer in the gate dielectric stack. This device exhibits excellent performance in both on and off states, with a maximum drain current of 510 μA μm-1 and a sub-thermionic subthreshold slope, and is essentially hysteresis-free. Negative differential resistance was observed at room temperature in the MoS2 negative-capacitance FETs as the result of negative capacitance due to the negative drain-induced barrier lowering. A high on-current-induced self-heating effect was also observed and studied.

Body-bias effect on drain-induced barrier lowering in sphere-shaped-recess cell-array transistor

Sphere-shaped-recess cell-array transistors (S-RCATs) have been playing a major role in DRAMs on the 70 nm design-rule. The S-RCAT has a recessed-channel structure that produces small drain-induced barrier lowering (DIBL) and large body-bias effect. The temperature and body-bias dependence of DIBL is studied for a S-RCAT. Negative DIBL is peculiarly observed under certain conditions. It is assumed that the negative DIBL originates from the increase of body-bias effect with increasing drain bias and temperature.