DIBL improvement in hysteresis-free and ferroelectric-gated FinFETs

Abstract

The improvement of drain-induced barrier lowering (DIBL) in hysteresis-free and ferroelectric-gated fin field effect transistors (FinFETs) [a.k.a., negative capacitance (NC) FinFET] has been experimentally verified. Moreover, all fabricated NC FinFETs (some of which are not hysteresis-free) have successfully shown sub-60-mV/decade subthreshold slope (SS) characteristics. By adjusting both the fin width and channel length, the ferroelectric and dielectric capacitance matching in the gate stacks of FinFETs is successfully implemented, resulting in hysteresis-free NC FinFETs with a 20 mV/decade SS. Finally, the negative DIBL phenomenon in the hysteresis-free NC FinFET has produced an enhanced DIBL of 20.78 mV/V (note that the DIBL of baseline FinFET is 68.89 mV/V at 300 K).