Experimental observation of zero DIBL in short-channel hysteresis-free ferroelectric-gated FinFET

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Abstract The experimental investigation for the drain-induced-barrier-lowering (DIBL) in nanometer scale hysteresis-free 100 nm-long ferroelectric-gated FinFET (which employs the voltage-amplifying attribute of Pb(Zr0.52Ti0.48)O3-based ferroelectric capacitor) is done to verify the DIBL improvement. The DIBL of the ferroelectric-gated FinFET (which is evaluated at 10−7 A/μm of drain current) is improved from ∼48 mV/V to ∼32 mV/V. When the DIBL is evaluated at 10−6 A/μm, it is reduced from 22.89 mV/V to ∼0 mV/V. The physical origin of the DIBL enhancement can be understood due to negative DIBL. The negative DIBL effect [a.k.a., drain-induced-barrier-rising (DIBAR)] is originated from a decrease of internal gate voltage, which takes place due to a gate charge reduction with increased drain voltage.