Steep-slope hysteresis-free negative capacitance MoS2 transistors.

The so-called Boltzmann Tyranny defines the fundamental thermionic limit of the subthreshold slope (SS) of a metal-oxide-semiconductor field-effect transistor (MOSFET) at 60 mV/dec at room temperature and, therefore, precludes the lowering of the supply voltage and the overall power consumption [1]. Adding a ferroelectric negative capacitor to the gate stack of a MOSFET may offer a promising solution to bypassing this fundamental barrier [2]. Meanwhile, two-dimensional (2D) semiconductors, such as atomically thin transition metal dichalcogenides (TMDs) due to their low dielectric constant, and ease of integration in a junctionless transistor topology, offer enhanced electrostatic control of the channel. Here, we combine these two advantages and demonstrate for the first time a molybdenum disulfide (MOS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> )2D steep slope transistor with a ferroelectric hafnium zirconium oxide layer (HZO) in the gate dielectric stack [3]. This device exhibits excellent performance in both on- and off-states, with maximum drain current of 510 μA/μm, sub-thermionic subthreshold slope and is essentially hysteresis-free. Negative differential resistance (NDR) was observed at room temperature in the MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> negative capacitance field-effect-transistors (NC-FETs) as the result of negative capacitance due to the negative drain-induced-barrier-lowering (DIBL). High on-current induced self-heating effect was also observed and studied. We will also discuss the effect of internal metal gate [4], [5], p-type 2D transistors [6], and ferroelectric switch speed issues [7] in this talk. The work is in close collaborations with Mengwei Si, Wonil Chung, Chun-Jung Su, Chunsheng Jiang, Hong Zhou, Kerry D. Maize, Ali Shakouri, Muhammad A. Alam.

The so-called Boltzmann Tyranny defines the fundamental thermionic limit of the subthreshold slope (SS) of a metal-oxide-semiconductor field-effect transistor (MOSFET) at 60 mV/dec at room temperature and, therefore, precludes the lowering of the supply voltage and the overall power consumption [1]. Adding a ferroelectric negative capacitor to the gate stack of a MOSFET may offer a promising solution to bypassing this fundamental barrier [2]. Meanwhile, two-dimensional (2D) semiconductors, such as atomically thin transition metal dichalcogenides (TMDs) due to their low dielectric constant, and ease of integration in a junctionless transistor topology, offer enhanced electrostatic control of the channel. Here, we combine these two advantages and demonstrate for the first time a molybdenum disulfide (MOS 2 )2D steep slope transistor with a ferroelectric hafnium zirconium oxide layer (HZO) in the gate dielectric stack [3]. This device exhibits excellent performance in both on- and off-states, with maximum drain current of $510 \mu \mathrm{A}/\mu \mathrm{m}$ , sub-thermionic subthreshold slope and is essentially hysteresis-free. Negative differential resistance (NDR) was observed at room temperature in the Mos2 negative capacitance field-effect-transistors (NC-FETs) as the result of negative capacitance due to the negative drain-induced-barrier-lowering (DIBL). High on-current induced self-heating effect was also observed and studied. We will also discuss the effect of internal metal gate [4], [5], p-type 2D transistors [6], and ferroelectric switch speed issues [7] in this talk. The work is in close collaborations with Mengwei Si, Wonil Chung, Chun-Jung Su, Chunsheng Jiang, Hong Zhou, Kerry D. Maize, Ali Shakouri, Muhammad A. Alam.

P-type two-dimensional steep-slope negative capacitance field-effect transistors are demonstrated for the first time with WSe2 as channel material and ferroelectric hafnium zirconium oxide in gate dielectric stack. F4-TCNQ is used as p-type dopant to suppress electron leakage current and to reduce Schottky barrier width for holes. WSe2 negative capacitance field-effect transistors with and without internal metal gate structures and the internal field-effect transistors are compared and studied. Significant SS reduction is observed in WSe2 negative capacitance field-effect transistors by inserting the ferroelectric hafnium zirconium oxide layer, suggesting the existence of internal amplification (∼10) due to the negative capacitance effect. Subthreshold slope less than 60 mV/dec (as low as 14.4 mV/dec) at room temperature is obtained for both forward and reverse gate voltage sweeps. Negative differential resistance is observed at room temperature on WSe2 negative capacitance field-effect-transistors as the result of negative capacitance induced negative drain-induced-barrier-lowering effect.

The so-called Boltzmann Tyranny defines the fundamental thermionic limit of the subthreshold slope (SS) of a metal-oxide-semiconductor field-effect transistor (MOSFET) at 60 mV/dec at room temperature and, therefore, precludes the lowering of the supply voltage and the overall power consumption. Adding a ferroelectric dielectric as a negative capacitor to the gate stack of a MOSFET may offer a promising solution to bypassing this fundamental barrier. Meanwhile, two-dimensional (2D) semiconductors, such as atomically thin transition metal dichalcogenides (TMDs) due to their low dielectric constant, and ease of integration in a junctionless transistor topology, offer enhanced electrostatic control of the channel. In this talk, we will review the recent progress on negative capacitance field-effect transistors (NC-FET) and ferroelectric field-effect transistors (Fe-FET) using TMDs as the transistor channels. [1,2] More importantly, a new device concept, which we call as ferroelectric semiconductor field-effect transistor (FeS-FET), was proposed and experimentally demonstrated. [3] In this novel FeS-FET, a 2D ferroelectric semiconductor α-In2Se3 is used to replace conventional semiconductor as channel. α-In2Se3 is identified due to its proper bandgap, room temperature ferroelectricity, the ability to maintain ferroelectricity down to a few atomic layers and the feasibility for large-area growth.[1] M. Si et al. Nature Nanotechnology 13, 24-28 (2018).[2] M. Si et al. 2017 IEDM, pp. 573-576 (2017).[3] M. Si et al. Nature Electronics 2, in press (2019).

In the last decade the power consumption of electronic devices has increased for both static and active components. Following the Dennard's scaling rule, as long as the transistor sizes are reduced then the supply voltage (VDD) can also be scaled in order to increase the area density and maintain or improve the performances. However, scaling VDD and thus shifting the threshold voltage (Vth) of 60mV in a metal-oxide semiconductor field-effect transistor (MOSFET) increases the OFF state current (Ioff ) by a factor of 10 in the ideal case. The reason for this is that the inverse subthreshold slope (SS) in an ideal MOSFET is limited by the thermionic emission of electrons over a potential barrier, which has an intrinsic physical limit of 60mV/decade. To overcome this limit, novel device concepts have been proposed and the tunnel field-effect transistor (TFET) is one of the most promising because it resembles a MOSFET and should enable to achieve sub-60mV/dec SS, low Ioff and small VDD. The aim of this thesis is to investigate the potential of TFETs by the fabrication and characterization of InAs/Si as p-channel and InAs/GaSb as n-channel device for a complementary TFET technology. III-V nanowires are grown via metal-organic chemical vapor deposition (MOCVD) and are integrated on Si(100) substrates using a novel technique called template-assisted selective epitaxy (TASE), which enables the fabrication of vertical and lateral III-V hetero-structure TFETs. Sub-40nm nanowire cross-section InAs/Si p-TFETs and InAs/GaSb n-TFETs in-plane on Si are demonstrated for the first time. The InAs/Si p-TFETs exhibit state-of-the art performances with an ON state current (Ion) of 4uA/um at VGS=VDS=-0.5V, ON/OFF ratio of 1x10E5 with SSavg of 70-80mV/dec at room temperature. The InAs/GaSb n-TFETs have an order of magnitude larger Ion but the SS is limited by the non-optimized gate-stack on InAs channel and by the depletion of the undoped GaSb source. Different operation regimes of TFETs are investigated by temperature-dependent measurements,Wentzel-Kramers-Brillouin (WKB) modeling and TCAD simulations, indicating that the switching region for InAs/Si is dominated by the presence of traps at the hetero-junction. The abruptness of the band-edges in InAs/GaSb is studied by the extraction of the conductance slope in fabricated p-n and p-i-n tunnel diodes.

The Moore’s law of scaling of metal oxide semiconductor field effect transistor (MOSFET) had been a driving force toward the unprecedented advancement in development of integrated circuit over the last five decades. As the technology scales down to 7 nm node and below following the Moore’s law, conventional MOSFETs are becoming more vulnerable to extremely high off-state leakage current exhibiting a tremendous amount of standby power dissipation. Moreover, the fundamental physical limit of MOSFET of 60 mV/decade subthreshold slope exacerbates the situation further requiring current transport mechanism other than drift and diffusion for the operation of transistors. One way to limit such unrestrained amount of power dissipation is to explore novel materials with superior thermal and electrical properties compared to traditional bulk materials. On the other hand, energy efficient steep subthreshold slope devices are the other possible alternatives to conventional MOSFET based on emerging novel materials. This dissertation addresses the potential of both advanced materials and devices for development of next generation energy efficient integrated circuits. Among the different steep subthreshold slope devices, tunnel field effect transistor (TFET) has been considered as a promising candidate after MOSFET. A superior gate control on source-channel band-to-band tunneling providing subthreshold slopes well below than 60 mV/decade. With the emergence of atomically thin two-dimensional (2D) materials, interest in the design of TFET based on such novel 2D materials has also grown significantly. Graphene being the first and the most studied among 2D materials with exotic electronic and thermal properties. This dissertation primarily considers current transport modeling of graphene based tunnel devices from transport phenomena to energy efficient integrated circuit design. Three current transport models: semi-classical, semi-quantum and numerical simulations are described for the modeling of graphene nanoribbon tunnel field effect transistor (GNR TFET) where the semi-classical model is in close agreement with the quantum transport simulation. Moreover, the models produced are also extended for integrated circuit design using Verilog-A hardware description language for logic design. In order to overcome the challenges associated with the band gap engineering for making graphene transistor for logic operation, the promise of graphene based interlayer tunneling transistors are discussed along with their existing fundamental physical limitation of subthreshold slope. It has been found that such interlayer tunnel transistor has very poor electrostatic gate control on drain current. It gives subthreshold slope greater than the thermionic limit of 60 mV/decade at room temperature. In order to resolve such limitation of

With the superior analog/RF performance of planar device architectures such as fully depleted silicon-on-insulator (FDSOI) MOSFETs, it becomes important to investigate the impact of a ferroelectric material in the gate stack, resulting in negative capacitance (NC) behavior, on the device performance. In this work, through calibrating the FDSOI MOSFET (as the baseline device architecture) with experimental data, we compare the impact of ferroelectric–dielectric (FE–DE) and ferroelectric–paraelectric–dielectric (FE–PE–DE) gate stacks on the electrostatics of an NCFET device for a practically realisable metal–ferroelectric–insulator–semiconductor (MFIS) structure. A suitable thickness of the ferroelectric (FE) layer in the FE–DE stack and the maximum drain–source voltage ( Vds ) that can be applied (determining the power supply voltage), are identified so as to ensure that constraints such as no negative differential resistance (NDR) effects, threshold voltage ( Vth ), sub-threshold slope (SS) invariability with drain voltage variations and hysteresis-free behavior in transfer characteristics ( Id – Vgs ) are all satisfied. From the thickness of the FE layer in the FE–DE stack, the thickness of the FE layer in the FE–PE–DE stack (PE layer thickness is fixed at 1 nm) is determined where with a thicker FE layer, we obtain similar capacitance from the FE–PE–DE gate stack to that obtained from the FE–DE stack, while meeting all the constraints applied to the FE–DE stack based NCFET, enabling determination of the power supply voltage. Through showing good SSs with reduced output conductance ( gds ), resulting in improved dc gain ( gmgds ) and improved linearity parameters ( gm2 and gm3 ) along with scaling of power supply, an FE–PE–DE stack shows better analog performance, with lower power consumption, compared to an FE–DE stack, for an FDSOI NCFET, at 14 nm gate length.

Since the end of Dennard scaling, where metal oxide semiconductor field effect transistor (MOSFET) operating frequency and energy efficiency improved with shrinking device dimensions [1], increasing transistor density is predicted to increase the total power consumption of a system [2]. A key limitation for MOSFETs is that the minimum rate of turn-on, or subthreshold swing (SS), is ~60 mV/decade at room temperature because of the Boltzmann statistics that dictate charge density. Thus, maintaining constant electric field without increasing energy consumption (i.e. gate bias) requires decreasing the SS by investigating alternative materials or device designs, like tunnel FETs (TFETs) [3]. Recent advances in atomic-scale control promise to provide control over quantum mechanical degrees of freedom which have hindered TFET performance in practice. These considerations make atomic precision advanced manufacturing (APAM) an appealing platform to realize a proof-of-concept TFET with atomic scale features [4,5].APAM can produce a 2D sheet of dopants in silicon beyond the solid solubility limit that can be patterned in-plane and capped with epitaxial silicon for strong carrier confinement in the out-of-plane direction (Figure 1). Indeed, improvements to planar TFETs that effectively have 1D channels with low on:off current ratios have been proposed by changing to a vertical geometry that leverages the carrier confinement afforded by 2D materials to create a 2D channel [6], though these materials are not typical in a silicon foundry. In contrast, APAM provides this carrier confinement while exclusively using materials and chemicals that are used in silicon foundries and with compatible processes [7]. In the APAM TFET (Figure 1.8.), a gate bias induces a layer of holes at the oxide/silicon interface that extends from the source, enabling tunneling between the 2D phosphorus-doped layer that comprise the drain and the 2D induced hole layer.As tunnelling occurs vertically through the epitaxial silicon cap, it becomes critical to determine the optimal growth temperature, to keep the dopants in a 2D sheet at low temperatures versus producing low-defect silicon at higher temperatures. Similarly, for optimal electric field control, it becomes critical to determine the optimal processing temperature to maintain the 2D dopant sheet and produce a low-defect gate oxide. The electronic thickness of the dopant layer can be measured using weak localization and the segregation of dopants out of the 2D sheet can be measured using secondary ion mass spectrometry. Our intial attemps at evaluating the electrical quality of the epitaxial silicon cap used PMOS transistors made with an ALD gate dielectric on APAM material without the buried phosphorus layer. Intuitively, we expect material grown at a higher temperature to produce a lower density of defects and therefore more performant PMOS, but find instead that the initial results demonstrate no systematic trend. These results potentially indicate there is an unknown variable obscuring the intentionally changed variable of growth temperature. Here, we propose several possible causes for this observation – both the variability from APAM processing or low-temperature microfabrication could mask an underlying trend.In summary, an APAM TFET provides a path toward increasing energy efficiency of transistors by decreasing SS compared to MOSFETs. The process tradeoffs that produce tightly confined 2D doped layers compared to low defect materials are starting to be explored using PMOS devices. Here, we report on the impact of process variability in drawing conclusions from these devices toward the realization of an APAM TFET.SNL is managed and operated by NTESS under DOE NNSA contract DE-NA0003525.[1] R. H. Dennard et al., “Design of ion-implanted MOSFET's with very small physical dimensions”, IEEE J. Solid-State Circuits 9, 256 (1974).[2] https://irds.ieee.org/[3] J. Koga et al., “Negative differential conductance in three‐terminal silicon tunneling device”, Applied Physics Letters, 69, 1435 (1996).[4] T.-M. Lu et al., “Path towards a vertical TFET enabled by atomic precision advanced manufacturing”, 2021 Silicon Nanoelectronics Workshop (2021).[5] X. Gao et al., “Modeling and Assessment of Atomic Precision Advanced Manufacturing (APAM) Enabled Vertical Tunneling Field Effect Transistor”, 2021 SISPAD, 102 (2021).[6] H. Lu et al., “Tunnel Field-Effect Transistors: State-of-the-Art”, IEEE J. Electron Device Society, 2, 44 (2014).[7] S. Misra et al., “Method of chemical doping that uses CMOS-compatible processes”, U.S. Patent 11,798,808. Figure 1

Reducing supply voltage is a promising way to address the power dissipation in nano-electronic circuits. However, the fundamental lower limit of subthreshold slope (SS) within metal oxide semiconductor field effect transistors (MOSFETs) is a major obstacle to further scaling the operation voltage without degrading ON/OFF ratio in current integrated circuits. Tunnel field-effect transistors (TFETs) benefit from steep switching characteristics due to the quantum-mechanical tunneling injection of carriers from source to channel, rather than by conventional thermionic emission in MOSFETs. TFETs based on group III-V compound semiconductor materials further improve the ON-state current and reduce SS due to the low band gap energies and smaller carrier tunneling mass. The mixed arsenide/antimonide (As/Sb) InxGa1-xAs/GaAsySb1-y heterostructures allow a wide range of band gap energies and various staggered band alignments depending on the alloy compositions in the source and channel materials. Band alignments at source/channel heterointerface can be well modulated by carefully controlling the compositions of the mixed As/Sb material system. In particular, this review introduces and summarizes the progress in the development and optimization of low-power TFETs using mixed As/Sb based heterostructures including basic working principles, design considerations, material growth, interface engineering, material characterization, device fabrication, device performance investigation, band alignment determination, and high temperature reliability. A review of TFETs using mixed As/Sb based heterostructures shows superior structural properties and distinguished device performance, both of which indicate the mixed As/Sb staggered gap TFET as a promising option for high-performance, low-standby power, and energy-efficient logic circuit application.

Scaling of semiconductor devices has pushed CMOS devices close to fundamental limits. The remarkable success story of Moore's law during the last 40 years, predicting the evolution of electronic device performances related to miniaturization, has always been respected. However, electron device challenges are now much more complex. In order to keep Moore's law living, device scaling-down is not enough. So called material and geometry technology boosters have been introduced. High-k dielectrics, silicon-on-insulator substrates or strained silicon are some booster examples, used at sub-micron scale. This work proposes an investigation of a hybrid CMOS/SET technology, based on gate-all-around silicon nanowires. It is shown that a silicon nanowire can serve two device purposes: first as innovative 3D metal-oxide-semiconductor field effect transistor (MOSFET), and second as single electron transistor (SET). The SET is a solid-state electronic device, which controls the transport of a unique or a few electrons. SET functions are not limited by its nano-scaled structure. The smaller is the better. SET consists of a small conductive quantum dot, called island, connected to two reservoirs acting as drain and source by tunnel junctions. The size of the island should be as small as possible – typical values ranging from 1 to 4nm – in order to have room temperature operation. Electron transport from source to island, and from island to drain is controlled by a capacitively coupled gate. The nano-scale size of the island makes the carrier electrostatic repulsion efficient. This effect is called Coulomb Blockade. SET advantages are an ultra-reduced size and a very low power consumption, while SET challenges are variability related to dimension control and background charge effect, room temperature operation and a reduced fan-out. The first chapter of this thesis introduces ideas of up-to-date MOS and SET devices and shows how to combine MOS and SET to obtain original electronic functions. The second chapter is a discussion of the nanowire as a technology platform for the integration of SET devices and also presents TCAD simulation results. Key contributions are reported in chapter three. This is the original and complete description of the different top-down processes used for the integration of a gate-all-around MOS/SET platform. Samples integrated at the EPFL Center of Microtechnology (CMI) are presented. Different approaches have been studied and used in order to overcome lithographic limitations, and to have a fast and reliable integration at moderate cost. This includes auto-aligned techniques, focused ion beam prototyping, and top-down local-SOI and true-SOI nanowires. The local-SOI technique based on silicon nano-channel wires has given the best results and offers a lot of flexibility in term of wire cross-sections and shapes. Gate-all-around silicon nanowires, obtained by sacrificial etching and self-limited oxidation, with a circular 5nm diameter cross-section have been characterized. Chapter four is the validation by measurements of both SET and MOS devices. Excellent room temperature characteristics have been observed in MOS structures, while both ID-VG Coulomb oscillations and ID-VD Coulomb gap are observed on smaller structures at cryogenic temperature (T<20K). The process described has many advantages in comparison with bottom-up grown wires, such an excellent crystallinity of the channel and ohmic source-drain contacts. Finite elements simulations have also highlighted the influence of carrier mobility, channel length and cross-section shape in our defined nanowire structures. The last chapter of this report concludes this work and gives perspectives on the near future. The hybrid combination of silicon nanowire MOSFET and SET can definitely be an appealing approach in order to bridge the gap between emerging nanoelectronic devices and more traditional CMOS.

A monolithically integrated Si interband tunneling diode (IBTD)/MOSFET memory for ultra low voltage operation below 0.5 V

Obtaining a subthreshold swing (SS) below the thermionic limit of 60 mV dec-1 by exploiting the negative-capacitance (NC) effect in ferroelectric (FE) materials is a novel effective technique to allow the reduction of the supply voltage and power consumption in field effect transistors (FETs). At the same time, two-dimensional layered semiconductors, such as molybdenum disulfide (MoS2), have been shown to be promising candidates to replace silicon MOSFETs in sub-5 nm-channel technology nodes. In this paper, we demonstrate NC MoS2 FETs by incorporating a ferroelectric Al-doped HfO2 (Al : HfO2), a technologically compatible material, in the FET gate stack. Al : HfO2 thin films were deposited on Si wafers by atomic layer deposition. Voltage amplification up to 1.25 times was observed in a FE bilayer stack of Al : HfO2/HfO2 with a Ni metallic intermediate layer. The minimum SS (SSmin) of the NC-MoS2 FET built on the FE bilayer improved to 57 mV dec-1 at room temperature, compared with SSmin = 67 mV dec-1 for the MoS2 FET with only HfO2 as a gate dielectric.

Bias temperature instability (BTI) in p+ poly-Si gated metal-oxide-semiconductor field-effect transistors (MOSFETs) with atomic-layer-deposited (ALD) Si-nitride/SiO2 stack gate dielectrics was systematically studied using drain current-gate voltage (Id-Vg) and modified direct-current current-voltage (DCIV) measurements. They exhibited quite unique behaviors as compared to the conventional SiON counterpart: turnaround of the threshold voltage shift (ΔVth) during stressing and significant positive BTI in nMOSFETs. The observed phenomena were consistently explained within the framework of conventional reaction-diffusion model for BTI but with two additional assumptions: (1) there exist pre-existing traps in the ALD Si-nitride/SiO2 stack dielectrics and (2) it is the inversion carriers (electrons or holes) rather than the accumulation carriers which effectively dissociate the SiH bonds at the SiO2∕Si interface during BTI stressing. Owing to the absence of nitrogen near the SiO2∕Si interface and the compensation effect on ΔVth between the charge trapping in the pre-existing traps and the dissociation of the SiH bonds under small voltage stress, the ALD Si-nitride/SiO2 stack dielectrics at the operating voltage may have similar or even longer BTI lifetime than the pure SiO2.

This paper describes an experimental comparative study of the matching between conventional (rectangular gate shape) and Diamond (hexagonal gate geometry) n-channel Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs), which were manufactured in an 130 nm Silicon-Germanium Bulk Complementary MOS (CMOS) technology and exposed to different X-rays Total Ionizing Doses (TIDs). The results indicate that the Diamond layout style with alpha () angle equal to 90˚ for MOSFETs is capable of boosting the device matching by at least 17% regarding the electrical pa-rameters studied (Threshold Voltage and Subthreshold Slope) as compared with the conventional MOSFET counterparts, considering that they present the same gate area, channel width, bias conditions and for the same TID. This is due to the Longitudinal Corner Effect (LCE). Parallel MOSFETs with Different Channel Length Effect (PAMDLE) and Deactivation of Parasitic MOSFETs in the Bird’s Beak Regions Effect (DEPAMBBRE) present in the structure of Diamond MOSFETs. Therefore, the Diamond layout style can be consid-ered an alternative hardness-by-design (HBD) layout strategy to boost the electrical performance and TID tolerance of MOSFETs enabling analog or radio-frequency CMOS inte-grated circuits (ICs) applications.

As scaling down the size of metal oxide semiconductor field-effect transistors (FETs), power dissipation has become a major challenge. Lowering down the sub-threshold swing (SS) is known as an effective technique to decrease the operating voltage of FETs and hence lower down the power consumption. However, the Boltzmann distribution of electrons (so-called ‘Boltzmann tyranny’) implements a physical limit to the SS value. Use of negative capacitance (NC) effect has enabled a new path to achieve a low SS below the Boltzmann limit (60 mV dec−1 at room temperature). In this work, we have demonstrated a NC-FET from an all two-dimensional (2D) metal ferroelectric semiconductor (MFS) vertical heterostructure: Graphene/CuInP2S6/MoS2. The negative capacitance from the ferroelectric CuInP2S6 has enabled the breaking of the ‘Boltzmann tyranny’. The heterostructure based device has shown steep slopes switching below 60 mV dec−1 (lowest to < 10 mV dec−1) over 3 orders of source-drain current, which provides an avenue for all 2D material based steep slope FETs.