Steep-Slope Hysteresis-Free Negative-Capacitance 2D Transistors

Abstract

The so-called Boltzmann Tyranny defines the fundamental thermionic limit of the subthreshold slope (SS) of a metal-oxide-semiconductor field-effect transistor (MOSFET) at 60 mV/dec at room temperature and, therefore, precludes the lowering of the supply voltage and the overall power consumption [1]. Adding a ferroelectric negative capacitor to the gate stack of a MOSFET may offer a promising solution to bypassing this fundamental barrier [2]. Meanwhile, two-dimensional (2D) semiconductors, such as atomically thin transition metal dichalcogenides (TMDs) due to their low dielectric constant, and ease of integration in a junctionless transistor topology, offer enhanced electrostatic control of the channel. Here, we combine these two advantages and demonstrate for the first time a molybdenum disulfide (MOS 2 )2D steep slope transistor with a ferroelectric hafnium zirconium oxide layer (HZO) in the gate dielectric stack [3]. This device exhibits excellent performance in both on- and off-states, with maximum drain current of $510 \mu \mathrm{A}/\mu \mathrm{m}$ , sub-thermionic subthreshold slope and is essentially hysteresis-free. Negative differential resistance (NDR) was observed at room temperature in the Mos2 negative capacitance field-effect-transistors (NC-FETs) as the result of negative capacitance due to the negative drain-induced-barrier-lowering (DIBL). High on-current induced self-heating effect was also observed and studied. We will also discuss the effect of internal metal gate [4], [5], p-type 2D transistors [6], and ferroelectric switch speed issues [7] in this talk. The work is in close collaborations with Mengwei Si, Wonil Chung, Chun-Jung Su, Chunsheng Jiang, Hong Zhou, Kerry D. Maize, Ali Shakouri, Muhammad A. Alam.