Negative Bias Temperature Instability Stress Research Articles

A modelling method of the on-state resistance of p-channel power MOSFETs under NBTI stress

Negative Bias Temperature Instability (NBTI) of p-channel power MOSFETs is a primary concern in gate oxide degradation. Instead of a qualitative conclusion, predicting the degradation in the on-state resistance during long-term operation is significant. This paper evaluates the degradation of each component of the on-state resistance under NBTI stress. By dividing the on-state resistance into two parts based on whether it is affected by NBTI, we obtain a first-order linear model form to model the on-state resistance. This study can support the physical modelling and the remaining useful life prediction of the on-state resistance in long-term operation.

Investigation of degradation and recovery characteristics of NBTI in 28-nm high-k metal gate process

Degradation induced by the negative bias temperature instability (NBTI) can be attributed to three mutually uncoupled physical mechanisms, i.e., the generation of interface traps (ΔV IT), hole trapping in pre-existing gate oxide defects (ΔV HT), and the generation of gate oxide defects (ΔV OT). In this work, the characteristic of NBTI for p-type MOSFET fabricated by using a 28-nm high-k metal gate (HKMG) process is thoroughly studied. The experimental results show that the degradation is enhanced at a larger stress bias and higher temperature. The effects of the three underlying subcomponents are evaluated by using the comprehensive models. It is found that the generation of interface traps dominates the NBTI degradation during long-time NBTI stress. Moreover, the NBTI parameters of the power-law time exponent and temperature activation energy as well as the gate oxide field acceleration are extracted. The dependence of operating lifetime on stress bias and temperature is also discussed. It is observed that NBTI lifetime significantly decreases as the stress increases. Furthermore, the decrease of charges related to interface traps and hole detrapping in pre-existing gate oxide defects are used to explain the recovery mechanism after stress.

Assessment of Negative Bias Temperature Instability Due to Interface and Oxide Trapped Charges in Gate-All-Around TFET Devices

The effects of negative bias temperature instability (NBTI) on emerging tunnel FET (TFET) devices are setting of important reliability concern for analog/digital circuit design. In this work, NBTI effects in gate-all-around tunnel FET (GAA TFET) devices have been thoroughly analyzed and the unstressed p-type GAA TFET transfer characteristics are calibrated with the experimentally published data to tune the models used for the numerical analysis. The GAA device is stressed for different time durations and for different temperatures to analyze the capture and emission probabilities of the trapped charges. The effect of oxide trapping, interface trapping, and trapping of charges at several regions in the channel are analyzed individually, as well as collectively. The sub-threshold voltage of the TFET device is also investigated and it has been found that the change in the sub-threshold slope is not at all degraded by NBTI stress.

Impact of Channel Thickness on the NBTI Behaviors in the Ge-OI pMOSFETs With Al2O3/GeOx Gate Stacks

The impact of channel thickness on the negative-bias temperature instability (NBTI) behaviors has been studied for the Germanium-on-Insulator (Ge-OI) pMOSFETs. It is found that the permanent and recoverable defects are generated simultaneously during the NBTI stress of Ge-OI pMOSFETs. The lower NBTI is confirmed for the Ge-OI pMOSFETs with a thinner channel, due to the reduction of the band bending of Ev under a fixed electrical field of NBTI stress. Thus, the channel thickness scaling could be an effective method to improve the NBTI reliability for Ge-OI pMOSFETs.

Comparative analysis of NBTI modeling frameworks BAT and Comphy

The Compact-Physical (Comphy) framework is tested against the experimental Negative Bias Temperature Instability (NBTI) data. A cost-function based optimizer is used for obtaining the parameters of Comphy. The ultrafast (10 μs delay) measured threshold voltage shift (ΔVT) during and after NBTI stress at various stress (VGSTR) and recovery (VGREC) bias, temperature (T) and stress time (tSTR), and mixed AC–DC stress using random VGSTR, VGREC, pulse duty cycle (PCD) and frequency (f) are used to test the model framework. The BTI Analysis Tool (BAT) framework, for which data from previous work is used, and Comphy are compared.

Pre-Silicon NBTI Delay-Aware Modeling of Network-on-Chip Router Microarchitecture

With enhancement of technology downscaling and packaging allows us to put more and more transistors within the same chip area. The Moore’s law still shows the growth in yield with increasing transistor density in deep sub-micron. This increment in transistor density encourages the computer architects to design Chip Multiprocessor (CMP) systems. In recent times, industry and researchers are focusing to add more cores per chip with increasing integration. The sharp growth in core numbers in System-on-Chip (SoC) raise intense challenges for communication among the cores. The scalability, fault tolerance and higher communication bandwidth features made Network-on-chip (NoC), a popular communication architecture than conventional bus architecture. However, the rapid shrinking of CMOS design margins in deep submicron technology has made aging mechanism such as Negative Bias Temperature Instability (NBTI), a prime concern in NoC design. In this paper, we propose a novel pre-silicon, NBTI stress aware circuit-to-system level solution for a reliable NoC router. To achieve reliability objective, we develop an NBTI aging-aware timing analysis framework based on the real workload stress. Our proposal is based on findings of most stressed path and cells due to NBTI induced effects. We develop an aging-aware cell library and used the multi Vdd technique to mitigate the NBTI induced delay effects. On the basis of volume of experimental analysis, we observed that 66.67% delay increases due to NBTI induced aging effects with real workload stress for a duration of five years. Our proposed NBTI stress mitigation algorithm and technique could able to reduce aging induced delay effects by 36%, hence enhancing the router performance under stress.

Investigation of degradation mechanism after negative bias temperature stress in Si/SiGe channel metal–oxide–semiconductor capacitors induced by hydrogen diffusion

In this research, based on I–V and C–V measurement at different temperatures, the interface defect density in the device with the Si/SiGe channel was discussed. In addition, negative bias temperature instability (NBTI) is also studied. In previous research, most of the flat-band voltage (V FB) shifts during NBTI stress was attributed to hole injection. In this article, however, the release of atomic hydrogen from the Si–H bonds at the SiO2/Si interface and at the SiGe interface produces a fixed oxide charge, which causes V FB shifts which vary with material.

Study of traps in low-temperature polysilicon thin film transistors using a current transient method

The trap characteristics of low-temperature polysilicon thin film transistors (TFTs) are studied using a current transient method that is based on the trapping and detrapping of charge carriers from the trap sites in the device. Analysis of the measured current transient curve allowed three types of detrapping behavior to be identified, each of which displayed a different time constant, activation energy, and spatial position. This current transient method can be integrated into the negative bias temperature instability stress test used for the reliability study. The peak amplitudes of the traps increase because of the stress applied in the test, thus demonstrating that the degradation mechanism of the TFTs is closely related to changes in the traps in these devices.

Recovery Behavior of Interface Traps After Negative Bias Temperature Instability Stress in p-FinFETs Featuring Fast Trap Characterization Technique

We present an experimental study on the recovery feature of generated interface traps (N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IT</sub> ) after the application of dc/ac negative-bias temperature instability (NBTI) stress in Si p-FinFETs using a fast direct-current current-voltage method. In addition to the delayed recovery that typically occurs after a 10-ms recovery time, the immediate recovery of N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> IT</sub> starting within a recovery time of 400 μs is observed, which is missing in the current reaction-diffusion model. In this study, this immediate recovery is systematically investigated under different stress modes and is attributed to the accumulation of H atoms. Furthermore, when the accumulated H atoms in a pulse-on phase are quickly consumed in the following pulse-off phase, a widely reported delayed recovery after Mode-B ac stress is observed.

Influence of Buried Oxide Si+ Implantation on TID and NBTI Effects for PDSOI MOSFETs

The total ionization dose (TID) effect and negative bias temperature instability (NBTI) effect of 130-nm partially-depleted silicon-on-insulator (PDSOI) MOSFETs fabricated on hardened wafers with silicon ion implantation and unhardened wafers are investigated. A TID-hardened PDSOI MOSFET up to 1 Mrad(Si) is obtained by Si+ implantation in buried oxide (BOX). The hardening benefits from the electron traps in the BOX introduced by Si+ implantation. Although the radiation hardening process has a rare impact on nominal electrical characteristics of the device before irradiation, it will affect the NBTI reliability, which is manifested as the decrease in the NBTI lifetime for the radiation-hardened devices. The energy distribution of positive charges built up during NBTI stress is obtained. It proves that more damage-related traps exist near the gate oxide/silicon interface for the radiation-hardened device, which accelerates the threshold voltage shift during the NBTI stress. This conclusion is also verified by the low-frequency noise characteristics.

Research on Negative Bias Temperature Instability Effects Under the Coupling of Total Ionizing Dose Irradiation for PDSOI MOSFETs

The degradation mechanisms for pMOSFETs from a 130 nm partially-depleted silicon on insulator (PDSOI) technology under the combined effects of total ionizing dose (TID) and negative bias temperature instability (NBTI) are investigated. The TID and NBTI related degradations show an opposite trend as gate oxide scaling, which implies the different traps are activated during irradiation and NBTI stress. The radiation-induced traps can affect the NBTI effect of pMOSFET, especially for the ON bias irradiation. The irradiated I/O pMOSFET shows a smaller threshold voltage shift than the un-irradiated device under the same NBTI stress at the early stress stage. It may be contributed to the enhanced Fowler-Nordheim electron injection during NBTI stressing after ON bias irradiation. But the irradiation also increases the time exponent $n$ from 0.11 to 0.13 for Core pMOSFETs and from 0.18 to 0.20 for I/O devices. It means that the NBTI degradations become worse after ON bias irradiation in a long time scale. This phenomenon is attributed to the change of trap characteristics caused by irradiation. As a result, the NBTI lifetime of Core device is reduced by nearly three orders of magnitude and the lifetime of I/O device is reduced by five times after ON bias irradiation at the rated operating voltage.

Time-Dependent Threshold Voltage Instability Mechanisms of p-GaN Gate AlGaN/GaN HEMTs Under High Reverse Bias Conditions

In this article, we experimentally investigate the degradation mechanisms of GaN high-electron mobility transistors (HEMTs) with p-type gate during long-term hightemperature reverse bias (HTRB) stress and negative bias temperature instability (NBTI) stress. Based on a number of stress/recovery experiments, we demonstrate that HTRB stress could lead to hole emission in the p-GaN layer, making threshold voltage (Vth) positively shift, while NBTI stress could result in detrapping at the AlGaN/GaN interface or the AlGaN layer and make Vth negatively shift. It is also found that the temperature rise can suppress the positive Vth shift and accelerate its recovery process in HTRB experiments.

Electrical performances degradations and physics based mechanisms under negative bias temperature instability stress for p-GaN gate high electron mobility transistors

In this paper, an in-depth evaluation of the negative bias temperature instability (NBTI) in p-GaN gate high electron mobility transistors with Schottky-type gate contact has been reported in detail. The measured results reveal that the threshold voltage (V th) positively shifts by 0.35 V and the on-state drain-source resistance (R dson) increases by 24.2 mΩ within 1 h at room temperature, even under the minimum allowed operating gate-voltage condition (V gs = −10 V) in the datasheet of the commercial device. With the help of energy band theory and experimental analyses, donor-type traps are demonstrated to dominate the degradation by reducing the positive charges in the p-GaN cap. Moreover, further quantitative analysis has been performed by the conductance–frequency measurements method. Considering the risk of degradation induced by NBTI, it turns necessary for the system designers to choose a more suitable negative bias operating condition so as to extend the robustness of the entire power system.

Improvement of negative bias temperature instability of LTPS TFTs by high pressure H2O annealing

In this study, high pressure H2O annealing (HPA) was performed to improve the reliability of low temperature poly-Si thin film transistors (LTPS TFTs) fabricated on a polyimide (PI) substrate. Due to the low heat resistance of the PI substrate, the pressure was high to reduce the temperature of the heat treatment. HPA was performed at 130 °C and 0.3 Mpa in an H2O ambient for 2 h. After HPA treatment, the threshold voltage (VT) shifted to the positive direction from −2.27 V to −1.75 V, and the hysteresis (ΔVT) decreased from 0.67 V to 0.24 V. The density of states (DOS) measurement shows that the interface trap decreased after HPA processing, hence, it is assumed that stability for bias stress has improved. Before and after HPA, the VT shift for negative bias temperature instability (NBTI) stress was 1.19 V and 0.2 V, respectively. After HPA treatment, ΔVT decreased significantly for bias stress. It seems that the decomposed oxygen from H2O diffused to the gate insulator and combined with Si to reduce the oxygen vacancy. The strength of the gate insulator improved after HPA.

Impacts of O2 Plasma on Negative Gate Bias Stress Instability of Tunnel Thin-Film Transistor

In this work, the impacts of oxygen (O2) plasma treatment on the performance and negative bias temperature instability (NBTI) of tunnel thin-film transistors (T-TFTs) with polycrystalline-silicon channel material are studied. After O2 plasma treatment, the T-TFT exhibits that the minimum leakage current is suppressed from 134 to 7 pA and the subthreshold swing (SS) is decreased from 0.602 to 0.508 V/decade. In addition, the degradation of SS and threshold voltage (VTH) of T-TFT with O2 plasma after NBTI stress for 1000 s are suppressed from 0.779 to 0.319 V/decade and 1.28 to -0.82 V, respectively. The degradation of on-state current is also improved significantly from -87% to -40% when the T-TFT is passivated by the O2 plasma. Moreover, the T-TFT with O2 plasma exhibits less stress voltage-dependent electrical degradation of NBTI than it without O2 plasma. When the stress voltage of NBTI increases, two-step VTH shift behavior of T-TFT with O2 plasma is observed due to the competition of hole trapping effect and SS degradation effect. Furthermore, the T-TFT with O2 plasma shows less electrical degradation quantity than it without O2 plasma when the temperature of NBTI is increased from 25 °C to 75 °C.

Gate Level NBTI and Leakage Co-Optimization in Combinational Circuits with Input Vector Cycling

Negative Bias Temperature Instability (NBTI) effect occurs in a PMOS transistor when turned ON leading to threshold voltage degradation. As sub-threshold leakage is significant in nanoscale CMOS circuits, input vector control can be employed wherein a Minimum Leakage Vector (MLV) is applied to the circuit during idle periods. In such a case, the ON PMOS transistors on the critical path are subject to NBTI stress for prolonged periods. Transistors can recover from stress when turned OFF. Based on this observation, we propose a vector cycling based leakage/NBTI co-optimization: a pair of MLVs are identified such that when applied alternately, on the critical path, PMOS transistors activated by one vector are turned OFF by the other vector. We employ Simulated Annealing (SA) for stochastic search of the first vector followed by back tracking to identify the second vector. Experimental results for a subset of ISCAS85 benchmarks implemented in 45 nm technology demonstrate the feasibility of vector cycling approach. When compared to leakage-only optimization, NBTI-only optimization, and co-optimization, on average, vector cycling yields 11, 3, and 6 percent NBTI improvements with 18, -9, and 4 percent leakage overheads respectively. The average area and dynamic power overheads are 13.78 and 0.15 percent respectively.

Understanding Frequency Dependence of Trap Generation Under AC Negative Bias Temperature Instability Stress in Si p-FinFETs

In this letter, we present an experimental study on the frequency ( f ) dependence of trap generation under AC negative bias temperature instability (NBTI) stress in Si p-channel fin field-effect transistors (p-FinFETs), by adopting the direct-current current voltage (DCIV) method and an energy profiling technique. The interface trap generation ( $\Delta ~\text{N}_{IT}$ ) and bulk trap generation ( $\Delta ~\text{N}_{OT}$ ) are separated from the measured DCIV data and their ${f}$ dependences are independently investigated. The DCIV results indicate that the observed strong ${f}$ dependence of trap generation is primarily attributed to the ${f}$ -dependent $\Delta ~\text{N}_{OT}$ that exhibits a 36% reduction when ${f}$ increases from 10 Hz to 1 MHz. Furthermore, this ${f}$ -dependent $\Delta ~\text{N}_{OT}$ is mainly distributed between ${\text{E}_{v}}$ and ${\text{E}_{i}}$ , and exhibits a visible ${f}$ -dependent peak of energy density around ${\text{E}_{c}}$ .

Investigation of the anomalous hump phenomenon in amorphous InGaZnO thin-film transistors

In this work, we investigated an anomalous hump in the bottom-gate amorphous-InGaZnO thin-film transistors. The hump in the subthreshold region appeared at elevated temperature and disappeared after N2 atmosphere annealing. The anomalous hump phenomenon is attributed to the existence of both main current path composed by electron and parasitic current path induced by positive charges formed by adsorbed H2O molecules. With the increase of the testing temperature, the hump effect becomes significant since the formation of positive charges is strengthened by heat. This hump can be weakened by negative bias temperature instability stress at high temperature due to the charge-trapping mechanism.

On Border Traps in Back-Side-Illuminated CMOS Image Sensor Oxides

CMOS image sensors (CISs) in back-side-illuminated configuration consist of photodiode arrays having metal lines and drive electronics beneath the active region with respect to the device/air interface so that the light reaches the photodiode active region directly. This enhances sensor quantum efficiency but reduces the electrical performance and reliability. The back-side configuration is realized by flipping the wafer upside down, bonding it to a handling wafer, mechanically thinning it, and opening a through-silicon via with a long plasma etch. As a result, gate oxides in back-side CISs show an increased density of donor-like border traps with respect to the conventional front-side-illuminated sensors. In this article, we try to add some information toward the comprehension of the origin and the electrical nature of those traps in back-side gate oxides. To this aim, we performed negative bias temperature instability stress on p-channel MOSFETs during which the traps were filled by holes tunneling from the substrate and then studied the relaxation transients of the drain current after the stress was removed. The characteristic emission times of a few specific levels were obtained at different temperatures. This allowed us to extract values of the trap activation energies, which resulted coherent with hole-capturing ${E}\,^{\prime }$ donor-like centers (trivalent silicon dangling bonds) commonly attributed to ionizing radiation.

Impacts of NBTI and hot-carrier stress on silicon nanowire transistor characteristics

Following the downscaling road map for planar metal–oxide–semiconductor field-effect transistors, non-planar (three-dimensional) multiple-gate architectures are becoming essential for the ultimate scaling of complementary metal–oxide–semiconductor devices. Gate-all-around (nanowire) field-effect transistors have proven to be the most suitable below-22 nm technology nodes. Hence the reliability of these devices is of great concern. Negative-bias temperature instability (NBTI) and hot-carrier degradation (HCD) are the key device reliability issues that exhibit some different features at nanoscale. In this work, the NBTI reliability issues of p-channel gate-all-around silicon nanowire transistors (SNWTs) under direct-current and alternating-current stress were investigated. When stressed, the NBTI behavior in SNWTs showed fast initial degradation, quick degradation saturation and then a special recovery behavior. Along with that, the effects of hot-carrier stress on n-channel SNWTs were studied. Due to the surrounded gate structure, it was observed that the effects of HCD were significant in the nanowire transistors.