Assessment of Negative Bias Temperature Instability Due to Interface and Oxide Trapped Charges in Gate-All-Around TFET Devices

Abstract

The effects of negative bias temperature instability (NBTI) on emerging tunnel FET (TFET) devices are setting of important reliability concern for analog/digital circuit design. In this work, NBTI effects in gate-all-around tunnel FET (GAA TFET) devices have been thoroughly analyzed and the unstressed p-type GAA TFET transfer characteristics are calibrated with the experimentally published data to tune the models used for the numerical analysis. The GAA device is stressed for different time durations and for different temperatures to analyze the capture and emission probabilities of the trapped charges. The effect of oxide trapping, interface trapping, and trapping of charges at several regions in the channel are analyzed individually, as well as collectively. The sub-threshold voltage of the TFET device is also investigated and it has been found that the change in the sub-threshold slope is not at all degraded by NBTI stress.