Pre-Silicon NBTI Delay-Aware Modeling of Network-on-Chip Router Microarchitecture

Abstract

With enhancement of technology downscaling and packaging allows us to put more and more transistors within the same chip area. The Moore’s law still shows the growth in yield with increasing transistor density in deep sub-micron. This increment in transistor density encourages the computer architects to design Chip Multiprocessor (CMP) systems. In recent times, industry and researchers are focusing to add more cores per chip with increasing integration. The sharp growth in core numbers in System-on-Chip (SoC) raise intense challenges for communication among the cores. The scalability, fault tolerance and higher communication bandwidth features made Network-on-chip (NoC), a popular communication architecture than conventional bus architecture. However, the rapid shrinking of CMOS design margins in deep submicron technology has made aging mechanism such as Negative Bias Temperature Instability (NBTI), a prime concern in NoC design. In this paper, we propose a novel pre-silicon, NBTI stress aware circuit-to-system level solution for a reliable NoC router. To achieve reliability objective, we develop an NBTI aging-aware timing analysis framework based on the real workload stress. Our proposal is based on findings of most stressed path and cells due to NBTI induced effects. We develop an aging-aware cell library and used the multi Vdd technique to mitigate the NBTI induced delay effects. On the basis of volume of experimental analysis, we observed that 66.67% delay increases due to NBTI induced aging effects with real workload stress for a duration of five years. Our proposed NBTI stress mitigation algorithm and technique could able to reduce aging induced delay effects by 36%, hence enhancing the router performance under stress.