Nanowire Tunnel FETs Research Articles

Rigorous Study on Hump Phenomena in Surrounding Channel Nanowire (SCNW) Tunnel Field-Effect Transistor (TFET)

In this paper, analysis and optimization of surrounding channel nanowire (SCNW) tunnel field-effect transistor (TFET) has been discussed with the help of technology computer-aided design (TCAD) simulation. The SCNW TFET features an ultra-thin tunnel layer at source sidewall and shows a high on-current (ION). In spite of the high electrical performance, the SCNW TFET suffers from hump effect which deteriorates subthreshold swing (S). In order to solve the issue, an origin of hump effect is analyzed firstly. Based on the simulation, the transfer curve in SCNW TFET is decoupled into vertical- and lateral-BTBTs. In addition, the lateral-BTBT causes the hump effect due to low turn-on voltage (VON) and low ION. Therefore, the device design parameter is optimized to suppress the hump effect by adjusting thickness of the ultra-thin tunnel layer. Finally, we compared the electrical properties of the planar, nanowire and SCNW TFET. As a result, the optimized SCNW TFET shows better electrical performance compared with other TFETs.

Nanowire Tunnel FET with Simultaneously Reduced Subthermionic Subthreshold Swing and Off-Current due to Negative Capacitance and Voltage Pinning Effects

Nanowire tunnel field-effect transistors (TFETs) have been proposed as the most advanced one-dimensional (1D) devices that break the thermionic 60 mV/decade of the subthreshold swing (SS) of metal oxide semiconductor field-effect transistors (MOSFETs) by using quantum mechanical band-to-band tunneling and excellent electrostatic control. Meanwhile, negative capacitance (NC) of ferroelectrics has been proposed as a promising performance booster of MOSFETs to bypass the aforementioned fundamental limit by exploiting the differential amplification of the gate voltage under certain conditions. We combine these two principles into a single structure, a negative capacitance heterostructure TFET, and experimentally demonstrate a double beneficial effect: (i) a super-steep SS value down to 10 mV/decade and an extended low slope region that is due to the NC effect and, (ii) a remarkable off-current reduction that is experimentally observed and explained for the first time by the effect of the ferroelectric dipoles, which set the surface potential in a slightly negative value and further blocks the source tunneling current in the off-state. State-of-the-art InAs/InGaAsSb/GaSb nanowire TFETs are employed as the baseline transistor and PZT and silicon-doped HfO2 as ferroelectric materials.

Implementation of ∑Δ ADC using electrically doped III‐V ternary alloy semiconductor nano‐wire TFET

In this work, a fast and low-power sigma delta ∑ Δ analogue-to-digital converter (ADC) has been developed using a hetero-material electrically-doped nano-wire tunnel field effect transistor (HM-ED-NW-TFET) for the first time. The better gate controllability of nano-wire and immunity against process variations of electrically doped tunnel field effect transistor (TFET) enhances resolution. In this regard, the first step that has been performed is the material engineering using A l x G a 1 − x Sb / GaA s 1 − y P y , to achieve significant driving current at low subthreshold swing and high I ON / I OFF ratio. Secondly, the mole fraction is optimised to upgrade the critical analogue component – the op-amp. Also, drain under lapping is included in p-TFET to bring its characteristics as close to n-TFET. Latter, the look-up tables of the proposed device has been generated which is used to develop individual block of ∑ Δ ADC in Cadence. The blocks are well verified and integrated into final ∑ Δ ADC and its performance is evaluated. Hence, this work has explored the inherent merits of HM-ED-NW-TFET in the development of low power and fast ∑ Δ ADC by virtue of a high slew rate op-amp. Therefore, this work contributes a novel approach to explore the characteristics of emerging devices in mixed signal applications.

Investigation of Line-edge Roughness Effects on Electrical Characteristics of Nanowire Tunnel FETs and MOSFETs

Investigation of Line-edge Roughness Effects on Electrical Characteristics of Nanowire Tunnel FETs and MOSFETs

Improved Drive Capability of Silicon Nano Tube Tunnel FET Using Halo Implantation

In this paper, we focus on the improvement of comprehensive device performance of Silicon Nanotube Tunnel Field Effect Transistor (NT_TFET) for ultra low power applications. In the design we have implanted 2nm Halo region at the source side of Si NT_TFET for improving the subthreshold swing and short channel effects (SCEs). To prove the concept, the performance of Silicon Nanowire tunnel FET (NW_TFET), Silicon Nanotube TFET without Halo (NT_TFET) and Silicon Nanotube TFET with halo (NT_FET_HALO) implant are compared. The impact of halo doping profile on the Subthreshold swing, ON and OFF current are investigated. Further, the degradation of OFF state current due to Halo doping is controlled by lightly doped drain.

Novel Design Approach of Extended Gate-On-Source Based Charge-Plasma Vertical-Nanowire TFET: Proposal and Extensive Analysis

While quenching the thirst of device scaling, it is utmost necessary not to compromise device performance. Thus, the scaling of tunnel devices is much efficient as compared to Field-Effect Transistors. A dopingless Nanowire (NW) Tunnel Field Effect Transistor (TFET) is proposed and analyzed in the submitted work. Intrinsic silicon is used as a base material for the NWTFET structure. The required doping for the proper working of TFET is induced by implementing the Charge-Plasmatechnique. The vertical NWTFET structure is scaled down to smaller dimensions to show the possibility and consistent performance of Nano-TFET devices. The proposed structure provides a better solution for the requirement of stringent conditions. The scaled-down source/drain length is kept equal to the Debye length to compensate for the need of abrupt junction at the source-channel interface. Several device parameters and analog characteristics are calculated to understand the proposed device behavior at different operating biases. The proposed deviceswitches with a steep subthreshold slope while maintaining ultra-low OFF-state current. The subthreshold slope is lowest for silicon-based TFET devices ever reported. The linearity parameters are calculated to check the effect of noise introduced within the device due to scaled-down dimensions. The proposeddevice is optimized by using Dual-Metal-Gate and Gate-On-Source technique. The achieved drain current is approx. 10 μA/μm for gate bias equal to 1 V.

Design and Analog Performance Analysis of Charge-Plasma Based Cylindrical GAA Silicon Nanowire Tunnel Field Effect Transistor

Due to the rigorous practice of scaling down the device technology, certain factors such as proper electrostatic controlling of the channel, dopingless substrate, and low thermal budget at the nanoscale are the keys to designing better, efficient and cost-effective semiconductor devices. In this paper, a Charge-Plasma (CP) based Gate-All-Around (GAA) Silicon Nanowire Tunnel Field Effect Transistor (NWTFET) is proposed. Charge-Plasma technique is used to induce electron and hole concentration within the drain/source regions respectively by depositing layers of metals with specific work functions. The RF and analog performance of Dopingless Gate-All-Around Silicon Nanowire Tunnel Field Effect Transistor (DL-GAA-NWTFET) are investigated and compared with Junctionless Gate-All-Around Silicon Nanowire Tunnel Field Effect Transistor (JL-GAA-NWTFET) and Conventional Gate-All-Around Silicon Nanowire Tunnel Field Effect Transistor (C-GAA-NWTFET). The RF/Analog performance parameters such as Unity Gain Frequency (fT), Total Gate Capacitance (Cgg), Intrinsic Gain (Av), Early Voltage (VEA), Output Transconductance (gds), Transconductance to Gain Factor (TGF) and Transconductance (gm) are analyzed, which shows the enhanced output characteristics of the DL-GAA-NWTFET compared to JL-GAA-NWTFET and C-GAA-NWTFET. DL-GAA-NWTFET also provides two-order high ON-state current to the OFF-state current ratio (ION/IOFF) with an enhancement of the other sensing parameters.

Design and Optimization of Germanium-Based Gate-Metal-Core Vertical Nanowire Tunnel FET.

In this paper, a germanium-based gate-metal-core vertical nanowire tunnel field effect transistor (VNWTFET) has been designed and optimized using the technology computer-aided design (TCAD) simulation. In the proposed structure, by locating the gate-metal as a core of the nanowire, a more extensive band-to-band tunneling (BTBT) area can be achieved compared with the conventional core–shell VNWTFETs. The channel thickness (Tch), the gate-metal height (Hg), and the channel height (Hch) were considered as the design parameters for the optimization of device performances. The designed gate-metal-core VNWTFET exhibits outstanding performance, with an on-state current (Ion) of 80.9 μA/μm, off-state current (Ioff) of 1.09 × 10−12 A/μm, threshold voltage (Vt) of 0.21 V, and subthreshold swing (SS) of 42.8 mV/dec. Therefore, the proposed device was demonstrated to be a promising logic device for low-power applications.

Performance Assessment of the Charge-Plasma-Based Cylindrical GAA Vertical Nanowire TFET With Impact of Interface Trap Charges

In this article, a charge-plasma (CP)-based gate-all-around (GAA) silicon vertical nanowire tunnel field-effect transistor (NWTFET) is proposed. The effects of interface trap charges (ITCs) on dopingless (DL) NW-based device have been addressed for the first time. CP technique is used to induce charge carriers within the drain/source regions by depositing layers of metals with specific work function. Linearity performance parameters such as higher order harmonic distortions (HDs), intermodulation distortions (IMDs), and interception points are calculated including the effects of ITCs on the cylindrical channel-surround gate-oxide interface. This work shows that positive ITCs can help in improving the device characteristics, whereas negative ITCs degrade the device performance. The ON-state current to OFF-state current ratio decreases for either polarity of ITCs. The ON-state current has been improved by approximately 50% with higher positive ITCs. The presence of positive ITCs in DL NWTFET improves the driving capability to be used for analog applications. The linearity parameters tend to improve with positive ITCs and degrade with negative ITCs. The proposed device has reached the same cutoff frequency at lower operating gate bias (approximately 0.8 V) with half the threshold voltage for higher positive ITCs.

Reducing ambipolar off-state leakage currents in III-V vertical nanowire tunnel FETs using gate-drain underlap

Tunnel Field-Effect Transistors (TFETs) are an emerging alternative to CMOS for ultralow power and neuromorphic applications. The off current (Ioff) and, hence, the subthreshold swing (S) in these devices are limited by ambipolarity, which degrades its capabilities in complementary circuits. Here, we investigate experimentally vertical InAs/InGaAsSb/GaSb nanowire TFETs with gate-drain underlap as a potential solution to avoid ambipolarity and study the temperature dependence of the tunneling current. We compare two different TFET designs, one with an underlap between the gate and drain and the other with an overlap. The introduction of a 25-nm-long underlap region reduced the minimum achievable current Imin from 92 pA/μm to 23 pA/μm by suppressing the ambipolarity and simultaneously improved the minimum S at room temperature from 46 mV/dec to 41 mV/dec at Vds = 0.1 V. We also observe a reduction in the measured on current (Ion) from 0.1 μA/μm in the overlapped device to 0.01 μA/μm in the underlapped device at a drain bias (Vds) = 0.1 V and Ioff = 1 nA/μm. Temperature dependent measurements reveal a potential barrier at the drain junction due to the ungated region at the underlap. We determine a barrier height of 63 meV at Vds = 0.1 V based on thermionic emission combined with a ballistic transport model. Thus, we conclude that gate placement on the drain side is crucial to obtain the low off-currents in TFETs required for ultralow power electronic applications but that the trade-off between Ion and Ioff has to be considered.

Design of NW TFET biosensor for enhanced sensitivity and sensing speed by using cavity extension and additional source electrode

A planer structure of a tunnel field effect transistor (TFET) faces many consequences of fabrication complexity and less controllability of the gate electrode over the channel. Therefore, in this Letter nanowire TFET (NW TFET) is presented for the biosensing application. For this purpose, a new design approach of NW TFET has been presented to overcome the issues of planer structure TFET and for improving sensitivity and sensing speed of the biosensor. In this concern, an addition electrode is placed around the source region and the cavity, which is generally created in the oxide region under the gate electrode, is extended towards the source oxide region. Thus, due to the presence of source electrode, additional holes are accumulated in the source surface region and forming a plasma layer of holes. Hence, abruptness at source/channel junction is created. So as the biomolecules enter into the cavity, the large variation is observed in electrostatic properties of the device due to different properties (dielectric/charge) of the biomolecules. These variations reflect as improved sensitivity of the biomolecule detector. Further to this, because of the supplementary source electrode, abrupt source/channel junction provides lower subthreshold swing, which reduces the response time of the device and increases the sensing speed of biomolecules detection.

Design and Investigation of Charge-Plasma-Based Work Function Engineered Dual-Metal-Heterogeneous Gate Si-Si0.55Ge0.45 GAA-Cylindrical NWTFET for Ambipolar Analysis

In this paper, we have proposed dopingless gate all around (GAA) nanowire tunnel field-effect transistor (NWTFET) made up of dual-material channel (DMaC). Charge-plasma (CP) technique is used to induce the doping concentration of charge carriers in the intrinsic semiconductor. GAA structure uses zirconium silicate (IV) (ZrSiO4)/silicon dioxide (SiO2) for heterogeneous gate (HG) structure metalized with two different gate metals. Auxiliary gate (GM1) and tunneling gate (GM2) have different work functions, i.e., $\phi _{1}$ and $\phi _{2}$ . The device physics is analyzed using electric field, charge carrier concentration, energy-band diagram, and tunneling rate across the structure. The effect of variation in $\phi _{1}$ and $\phi _{2}$ helps in the analysis of the ambipolar and analog behavior of the proposed device CP-dual metal-HG-DMaC-NWTFET. The reported ON-state current is $5.54~\mu \text{A}/\mu \text{m}$ , and the OFF-state current is approximately 0.1 aA/ $\mu \text{m}$ . The proposed device showed negligible ambipolar current (10−19 A/ $\mu \text{m}$ ) as negative bias increases to $V_{\mathbf {GS}} =-0.8$ V making the device compatible for low-voltage applications.

Fabrication Methods for Nanowire Tunnel FET with Locally Concentrated Silicon-germanium Channel

Fabrication Methods for Nanowire Tunnel FET with Locally Concentrated Silicon-germanium Channel

Random Dopant-Induced Variability in Si-InAs Nanowire Tunnel FETs: A Quantum Transport Simulation Study

In this letter, we report a quantum transport simulation study of the impact of random discrete dopants (RDDs) on Si-InAs nanowire p-type Tunnel FETs. The band-to-band tunneling is simulated using the non-equilibrium Green’s function formalism in effective mass approximation, implementing a two-band model of the imaginary dispersion. We have found that RDDs induce strong variability not only in the OFF-state but also in the ON-state current of the TFETs. Contrary to the nearly normal distribution of the RDD-induced ON-current variations in conventional CMOS transistors, the TFET’s ON-currents variations are described by a logarithmic distribution. The distributions of other figures of merit (FoM) such as threshold voltage and subthreshold swing are also reported. The variability in the FoM is analyzed by studying the correlation between the number and the position of the dopants.

Impact of source doping on the performance of vertical InAs/InGaAsSb/GaSb nanowire tunneling field-effect transistors

In this paper, we analyze experimental data from state-of-the-art vertical InAs/InGaAsSb/GaSb nanowire tunneling field-effect transistors (TFETs) to study the influence of source doping on their performance. Overall, the doping level impacts both the off-state and on-state performance of these devices. Separation of the doping from the heterostructure improved the subthreshold swing of the devices. The best devices reached a point subthreshold swing of 30 mV/dec at 100 x higher currents than previous Si-based TFETs. However, separation of doping from the heterostructure had a significant impact on the on-state performance of these devices due to effects related to source depletion. An increase in the doping level helped to improve the on-state performance, which also increased the subthreshold swing. Thus, further optimization of doping incorporation with the heterostructure will help to improve vertical InAs/InGaAsSb/GaSb nanowire TFETs.

Vertical Nanowire TFETs With Channel Diameter Down to 10 nm and Point SMIN of 35 mV/Decade

We present experimental data from vertical InAs/InGaAsSb/GaSb nanowire tunnel field-effect transistors with channel diameter scaled down to 10 nm and ability to reach a point subthreshold swing of 35 mV/decade at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = 0.05 V. Furthermore, the impact of drain, channel, and source diameter scaling on the subthreshold swing and currents are studied. Impact of gate-overlap is more evident for devices with highly scaled source due to strong reduction of the current. Furthermore, small channel diameter makes these devices more susceptible to random telegraph signal noise.

Capacitance Measurements in Vertical III–V Nanowire TFETs

By measuring scattering parameters over a wide range of bias points, we study the intrinsic gate capacitance as well as the charge partitioning of vertical nanowire tunnel field-effect transistors (TFETs). The gate-to-drain capacitance ${C} _{ {gs}}$ is found to largely dominate the ON-state of TFETs, whereas the gate-to-source capacitance ${C} _{ {gs}}$ is sufficiently small to be completely dominated by the parasitic components. This indicates that the tunnel junction on the source side almost completely decouples the channel charge from the small-signal variation in the source, while the absence of a tunnel junction on the drain side allows the channel charge to follow the drain small-signal variation much more directly.

Numerical analysis of band tails in nanowires and their effects on the performance of tunneling field-effect transistors

Band tails in heavily doped semiconductors are one of the important parameters that determine transfer characteristics of tunneling field-effect transistors. In this study, doping concentration and doing profile dependences of band tails in heavily doped Si nanowires were analyzed by a nonequilibrium Green function method. From the calculated band tails, transfer characteristics of nanowire tunnel field-effect transistors were numerically analyzed by Wentzel–Kramer–Brillouin approximation with exponential barriers. The calculated transfer characteristics demonstrate that the band tails induced by dopants degrade the subthreshold slopes of Si nanowires from 5 to 56 mV/dec in the worst case. On the other hand, surface doping leads to a high drain current while maintaining a small subthreshold slope.

Strained Silicon Single Nanowire Gate-All-Around TFETs with Optimized Tunneling Junctions

In this work, we demonstrate a strained Si single nanowire tunnel field effect transistor (TFET) with gate-all-around (GAA) structure yielding Ion-current of 15 μA/μm at the supply voltage of Vdd = 0.5V with linear onset at low drain voltages. The subthreshold swing (SS) at room temperature shows an average of 76 mV/dec over 4 orders of drain current Id from 5 × 10−6 to 5 × 10−2 µA/µm. Optimized devices also show excellent current saturation, an important feature for analog performance.

Simulation and comparative study on analog/RF and linearity performance of III–V semiconductor-based staggered heterojunction and InAs nanowire(nw) Tunnel FET

This paper presents the comparative study on linearity and analog/radio frequency presentation of an III–V staggered hetero-junction nanowire (NW) TFET with Si and InAs based NW TFET of same dimension. The device parameter of analog/RF performance for low power application such as transconductance (gm), output resistance (RO), intrinsic gain (gmR0), cut-off frequency (fT), maximum frequency of oscillation (fmax), gain bandwidth product (GBW), VIP2, VIP3 as well as 1-dB compression point has been explored. There is a better improvement in analog/radio frequency presentation obtained from heterojunction NW TFET over Si and InAs TFET. The result reveals that heterojunction TFET provides superior intrinsic gain, higher cutoff frequency, higher GBW better linearity performance as compared to Si and InAs TFET.