Novel Design Approach of Extended Gate-On-Source Based Charge-Plasma Vertical-Nanowire TFET: Proposal and Extensive Analysis

Abstract

While quenching the thirst of device scaling, it is utmost necessary not to compromise device performance. Thus, the scaling of tunnel devices is much efficient as compared to Field-Effect Transistors. A dopingless Nanowire (NW) Tunnel Field Effect Transistor (TFET) is proposed and analyzed in the submitted work. Intrinsic silicon is used as a base material for the NWTFET structure. The required doping for the proper working of TFET is induced by implementing the Charge-Plasmatechnique. The vertical NWTFET structure is scaled down to smaller dimensions to show the possibility and consistent performance of Nano-TFET devices. The proposed structure provides a better solution for the requirement of stringent conditions. The scaled-down source/drain length is kept equal to the Debye length to compensate for the need of abrupt junction at the source-channel interface. Several device parameters and analog characteristics are calculated to understand the proposed device behavior at different operating biases. The proposed deviceswitches with a steep subthreshold slope while maintaining ultra-low OFF-state current. The subthreshold slope is lowest for silicon-based TFET devices ever reported. The linearity parameters are calculated to check the effect of noise introduced within the device due to scaled-down dimensions. The proposeddevice is optimized by using Dual-Metal-Gate and Gate-On-Source technique. The achieved drain current is approx. 10 μA/μm for gate bias equal to 1 V.