Multiple-valued Logic Research Articles

Controllable potential barrier for multiple negative-differential-transconductance and its application to multi-valued logic computing

Various studies on multi-valued-logic (MVL) computing, which utilizes more than two logic states, have recently been resumed owing to the demand for greater power saving in the current logic technologies. In particular, unlike old-fashioned researches, extensive efforts have been focused on implementing single devices with multiple threshold voltages via a negative-differential current change phenomenon. In this work, we report a multiple negative-differential-transconductance (NDT) phenomenon, which is achieved through the control of partial gate potential and light power/wavelength in a van-der-Waals (vdW) multi-channel phototransistor. The partial gating formed a controllable potential barrier/well in the vdW channel, enabling control over the collection of carriers and eventually inducing the NDT phenomenon. Especially, the strategy shining lights with different powers/wavelengths facilitated the precise NDT control and the realization of the multiple NDT phenomenon. Finally, the usability of this multiple NDT device as a core device of MVL arithmetic circuits such as MVL inverters/NAND/NOR gates is demonstrated.

TQCAsim: An Accurate Design and Essential Simulation Tool for Ternary Logic Quantum-Dot Cellular Automata

Having a reliable simulation tool for evaluating the performance of each design is indispensable. Designing multiple-valued logic (MVL) systems help to overcome the limitations existing in binary systems. Quantum-dot cellular automata (QCA) is a technology that can be substituted for CMOS in MVL designs. This paper represents an exquisite software platform for designing and simulating circuits which are restricted to three-valued logic (Ternary) quantum-dot cellular automata (QCA). Working with TQCAsim is so convenient because it can run in both Windows or Linux based computers. It has a tenacious simulation engine that can warranty precise results. This tool shows the results in graphical formats. As well, designers can easily layout their ternary QCA designs by using various sets of CAD tools. In this paper, the ternary model of QCA and its energy calculation will be demonstrated. The simulation Process will be explained step by step. MIN, MAX, NOT, and XOR gates had been simulated already by this software.

Low-Threshold II–VI Lattice-Matched SWS-FETs for Multivalued Low-Power Logic

The aim of this paper is to design low-threshold variation, four-state/two-bit Si/SiGe quantum-well n- and p-channel spatial wavefunction-switched field-effect transistors (SWS-FETs). This is achieved by incorporating high-k lattice-matched ZnS–ZnMgS gate dielectric layers resulting in low interface charge. Quantum simulations show switching of electron wavefunction from the lower to the upper Si quantum well in the n-channel as the gate voltage is increased. In the p-channel case, the hole wavefunction switches from the upper to the lower SiGe quantum well. The novelty is in the use of high-mobility metal-oxide-semiconductor (MOS)-gate modulation-doped (MOD) SWS-FETs. The low-threshold lattice-matched gate insulator SWS-FETs are scalable to sub-7 nm and are compatible with quantum-dot nonvolatile random-access memories (QD-NVRAMs). In terms of multivalued logic (MVL) gates, our circuit simulations using the Berkeley Short-channel IGFET Model (BSIM)-based analog behavioral model (ABM) have shown two-bit/four-state output–input transfer characteristics in SWS-complementary metal oxide semiconductor (CMOS) inverters having two Si/SiGe quantum-well channels. In addition, two-bit static random-access memories (SRAMs) are designed, resulting in significantly reduced FET count and power dissipation. Finally, integration of multivalued SWS-CMOS logic, multibit QD-NVRAM cells, and SWS-based SRAMs and registers is presented.

Recent Advances on Multivalued Logic Gates: A Materials Perspective.

The recent advancements in multivalued logic gates represent a rapid paradigm shift in semiconductor technology toward a new era of hyper Moore's law. Particularly, the significant evolution of materials is guiding multivalued logic systems toward a breakthrough gradually, whereby they are transcending the limits of conventional binary logic systems in terms of all the essential figures of merit, i.e., power dissipation, operating speed, circuit complexity, and, of course, the level of the integration. In this review, recent advances in the field of multivalued logic gates based on emerging materials to provide a comprehensive guideline for possible future research directions are reviewed. First, an overview of the design criteria and figures of merit for multivalued logic gates is presented, and then advancements in various emerging nanostructured materials—ranging from 0D quantum dots to multidimensional heterostructures—are summarized and these materials in terms of device design criteria are assessed. The current technological challenges and prospects of multivalued logic devices are also addressed and major research trends are elucidated.

New Design of Binary to Ternary Converter

Ternary quantum-dot cell automata (TQCA) are a relatively new quantum structure in QCA. The design of ternary digital circuits with this type of structure is increasing because of its proximity to fuzzy logic. The use of multi value logic (MVL) increases circuit density and gives more information about the variable. Designing a circuit combined of binary QCA (bQCA) and TQCA requires interaction between these two technologies, and to create this interaction a converter is used to convert binary to ternary, which is a useful interface. In fact, binary to ternary design can be used as a link between QCA technology at various levels and new multi-value QCA cell structures can be used. In this paper, a new binary-to-ternary converter is introduced. The proposed circuit simulation is presented to show the correct performance of the proposed converter by MATLAB software.

GÖDEL ON MANY-VALUED LOGIC

AbstractThis paper collects and presents unpublished notes of Kurt Gödel concerning the field of many-valued logic. In order to get a picture as complete as possible, both formal and philosophical notes, transcribed from the Gabelsberger shorthand system, are included.

From Boolean Valued Analysis to Quantum Set Theory: Mathematical Worldview of Gaisi Takeuti

Gaisi Takeuti introduced Boolean valued analysis around 1974 to provide systematic applications of the Boolean valued models of set theory to analysis. Later, his methods were further developed by his followers, leading to solving several open problems in analysis and algebra. Using the methods of Boolean valued analysis, he further stepped forward to construct set theory that is based on quantum logic, as the first step to construct "quantum mathematics", a mathematics based on quantum logic. While it is known that the distributive law does not apply to quantum logic, and the equality axiom turns out not to hold in quantum set theory, he showed that the real numbers in quantum set theory are in one-to-one correspondence with the self-adjoint operators on a Hilbert space, or equivalently the physical quantities of the corresponding quantum system. As quantum logic is intrinsic and empirical, the results of the quantum set theory can be experimentally verified by quantum mechanics. In this paper, we analyze Takeuti’s mathematical world view underlying his program from two perspectives: set theoretical foundations of modern mathematics and extending the notion of sets to multi-valued logic. We outlook the present status of his program, and envisage the further development of the program, by which we would be able to take a huge step forward toward unraveling the mysteries of quantum mechanics that have persisted for many years.

Complementary Driving between 2D Heterostructures and Surface Functionalization for Surpassing Binary Logic Devices.

Recently, for overcoming the fundamental limits of conventional silicon technology, multivalued logic (MVL) circuits based on two-dimensional (2D) materials have received significant attention for reducing the power consumption and the complexity of integrated circuits. Compared with the conventional silicon complementary metal oxide semiconductor technology, new functional heterostructures comprising 2D materials can be readily implemented, owing to their unique inherent electrical properties. Furthermore, their process integration does not pose issues of lattice mismatch at junction interfaces. This facilitates the realization of new functional logic gate circuit configurations. However, the reported three-valued NOT gates (ternary inverters) based on 2D materials require stringent operating conditions and complex fabrication processes to obtain three distinct logic states. Herein, a general structure of MVL devices based on a simple series connection of 2D materials with partial surface functionalization is demonstrated. By arranging three 2D materials exhibiting p-type, ambipolar, and n-type conductivities, ternary inverter circuits can be established based on the complementary driving between 2D heterotransistors. This ternary inverter circuit can be further improved for quaternary inverter circuits by controlling the charge neutral point of partial ambipolar 2D materials using surface functionalization, which is an effective and nondestructive doping method for 2D materials.

What Is That To You?

What Is That To You?

Ideals in residuated lattices

"The notion of ideal in residuated lattices is introduced in [Kengne, P. C., Koguep, B. B., Akume, D. and Lele, C., L-fuzzy ideals of residuated lattices, Discuss. Math. Gen. Algebra Appl., 39 (2019), No. 2, 181–201] and [Liu, Y., Qin, Y., Qin, X. and Xu, Y., Ideals and fuzzy ideals in residuated lattices, Int. J. Math. Learn & Cyber., 8 (2017), 239–253] as a natural generalization of that of ideal in MV algebras (see [Cignoli, R., D’Ottaviano, I. M. L. and Mundici, D., Algebraic Foundations of many-valued Reasoning, Trends in Logic-Studia Logica Library 7, Dordrecht: Kluwer Academic Publishers, 2000] and [Chang, C. C., Algebraic analysis of many-valued logic, Trans. Amer. Math. Soc., 88 (1958), 467–490]). If A is an MV algebra and I is an ideal on A then the binary relation x ∼I y iff x^{*}Ꙩ y; x Ꙩy^{*} ∈ I , for x; y ∈ A; is a congruence relation on A. In this paper we find classes of residuated lattices for which the relation ∼ I (defined for MV algebras) is a congruence relation and we give new characterizations for i-ideals and prime i-ideals in residuated lattices. As a generalization of the case of BL algebras (see [Lele, C. and Nganou, J. B., MV-algebras derived from ideals in BL-algebras, Fuzzy Sets and Systems, 218 (2013), 103–113]), we investigate the relationship between i-ideals and deductive systems in residuated lattices."

Ultra low power design of multi-valued logic circuit for binary interfaces

From the dawn of the computer age, man has mass produced binary components for computers, due to which ternary or higher radix computers are not yet commercially used. It has been proved that ternary logic can be more efficient than binary logic and there are many devices in development that operate on more than two internal states. Therefore an efficient method to produce multi-valued logic on the basis of binary input provided is needed. In this article, an effective, simple, flexible, and low power consumption implementation has been proposed that can convert any binary number to a number of chosen radix. The proposed design is implemented in 32 nm TSMC CMOS. The proposed design is then evaluated in power/delay space and its performances are compared with the latest state of art designs. The proposed circuit exhibits power saving up to 92% over previous models.

RAPID: a knowledge-based assistant for designing web APIs

With the rise in initiatives such as software ecosystems and Internet of Things (IoT), developing web Application Programming Interfaces (web APIs) has become an increasingly common practice. One main concern in developing web APIs is that they expose back-end systems and data toward clients. This exposure threatens critical non-functional requirements, such as the security of back-end systems, the performance of provided services, and the privacy of communications with clients. Although dealing with non-functional requirements during software design has been long studied, there is still no framework to specifically assist software developers in addressing these requirements in web APIs. In this paper, we introduce Rational API Designer (RAPID), an open-source assistant that advises on designing non-functional requirements in the architecture of web APIs. We have equipped RAPID with a broad range of expert knowledge about API design, systematically collected and extracted from the literature. The API design knowledge has been encoded as a set of 156 rules using the Non-Functional Requirements (NFR) multi-valued logic, a formal framework commonly used to describe non-functional and functional requirements of software systems. RAPID uses the encoded knowledge in a stepwise inference procedure to arrive from a given requirement, to a set of design alternatives to a final recommendation for a given API design specification. Seven well-experienced software engineers have blindly evaluated the accuracy of RAPID’s consultations over seven different cases of web API design and on providing design guidelines for thirty design questions. The results of the evaluation show that RAPID’s recommendations meet acceptable standards of the majority of the evaluators 73.3% of the time. Moreover, analysis of the evaluators’ comments suggests that more than one-third of the unacceptable ratings (33.8%) given to RAPID’s answers are due to valid but incomplete design guidelines. We thus expect that the accuracy of the consultations will increase as RAPID’s knowledge of API design is extended and refined.

Radix-p Multiple Valued Logic Function Simplification using Higher Radix Representation

Conventional Boolean logic, which is based on radix-2 binary logic, is no longer suitable to represent complex digital systems. As digital systems continue to grow in complexity, more compact representations become essential to describe these systems. One such possibility is to use multiple-valued logic, with radices larder than two. Many non-conventional technologies are considered as candidates to replace conventional semiconductor based switching circuit technology for computational systems such. Interestingly, some of these technologies are inherently multiple valued. Multiple-valued logic design and optimization methodologies are not yet elaborated, as compared to the well-established binary logic design and optimization and testing scheme. In this paper we are proposing an algorithm, with which functions to describe digital systems are specified and simplified using Multiple valued logic. Representing a digital system with different radices come out with different equivalent specifications for that system. A designer can choose the most suitable specification for his design constrains. The influence of radix increase on the complexity of the algorithm and the resulting specification is also demonstrated and discussed in this paper.

Investigation of Multiple-valued Logic Technologies for Beyond-binary Era

Computing technologies are currently based on the binary logic/number system, which is dependent on the simple on and off switching mechanism of the prevailing transistors. With the exponential increase of data processing and storage needs, there is a strong push to move to a higher radix logic/number system that can eradicate or lessen many limitations of the binary system. Anticipated saturation of Moore’s law and the necessity to increase information density and processing speed in the future micro and nanoelectronic circuits and systems provide a strong background and motivation for the beyond-binary logic system. In this review article, different technologies for Multiple-valued-Logic (MVL) devices and the associated prospects and constraints are discussed. The feasibility of the MVL system in real-world applications rests on resolving two major challenges: (i) development of an efficient mathematical approach to implement the MVL logic using available technologies, and (ii) availability of effective synthesis techniques. This review of different technologies for the MVL system is intended to perform a comprehensive investigation of various MVL technologies and a comparative analysis of the feasible approaches to implement MVL devices, especially ternary logic.

Energy-Efficient and PVT-Tolerant CNFET-Based Ternary Full Adder Cell

Full adder cell is an important module in arithmetic and processing systems whose performance has a great impact on performance of the whole system. By continuous scaling of the MOS transistors, some challenges and problems appear such as high leakage dissipation for which emerging technologies have been studied as a solution. Carbon nanotube field effect transistor (CNFET) is one of the most potential alternatives for the traditional MOSFET. The threshold voltage of a CNFET can be adjusted by tuning its CNT diameter. This property makes them to be appropriate for designing voltage mode multi-valued logic circuits. In this paper, a novel multiplexer-based ternary full adder cell using CNFET is presented. The proposed circuit is simulated and compared with the state-of-the-art designs using Synopsys HSPICE simulator. Simulations are done to investigate the effect of process (P), voltage (V) and temperature (T) variations on the circuit. The results show that the proposed design reduces the energy consumption by about 54% than the best reported design, while is robust against PVT variations.

Carbon Nanotube Field Effect Transistor (CNTFET) and Resistive Random Access Memory (RRAM) Based Ternary Combinational Logic Circuits

The capability of multiple valued logic (MVL) circuits to achieve higher storage density when compared to that of existing binary circuits is highly impressive. Recently, MVL circuits have attracted significant attention for the design of digital systems. Carbon nanotube field effect transistors (CNTFETs) have shown great promise for design of MVL based circuits, due to the fact that the scalable threshold voltage of CNTFETs can be utilized easily for the multiple voltage designs. In addition, resistive random access memory (RRAM) is also a feasible option for the design of MVL circuits, owing to its multilevel cell capability that enables the storage of multiple resistance states within a single cell. In this manuscript, a design approach for ternary combinational logic circuits while using CNTFETs and RRAM is presented. The designs of ternary half adder, ternary half subtractor, ternary full adder, and ternary full subtractor are evaluated while using Synopsis HSPICE simulation software with standard 32 nm CNTFET technology under different operating conditions, including different supply voltages, output load variation, and different operating temperatures. Finally, the proposed designs are compared with the state-of-the-art ternary designs. Based on the obtained simulation results, the proposed designs show a significant reduction in the transistor count, decreased cell area, and lower power consumption. In addition, due to the participation of RRAM, the proposed designs have advantages in terms of non-volatility.

A Novel Design of Octal-Valued Logic Full Adder Using Light Color State Model

Due to the demand of high computational speed for processing big data that requires complex data manipulations in a timely manner, the need for extending classical logic to construct new multi-valued optical models becomes a challenging and promising research area. This paper establishes a novel octal-valued logic design model with new optical gates construction based on the hypothesis of Light Color State Model to provide an efficient solution to the limitations of computational processing inherent in the electronics computing. We provide new mathematical definitions for both of the binary OR function and the PLUS operation in multi valued logic that is used as the basis of novel construction for the optical full adder model. Four case studies were used to assure the validity of the proposed adder. These cases proved that the proposed optical 8-valued logic models provide significantly more information to be packed within a single bit and therefore the abilities of data representation and processing is increased.

Nonlinearity of Many-Valued Logic Component Functions of Modern Cryptographic Algorithms S-boxes

Block symmetric cryptographic algorithms are the essential and inalienable element of any information security system. The main component of block symmetric cryptographic algorithms is the S-box, which largely determines the speed and cryptographic quality of the entire cryptographic transformation. The rapid development of cryptanalysis methods, including the development of quantum computers, requires a more careful research of all possible representations of nonlinear elements of block symmetric cryptographic algorithms. In view of the fact that in addition to the mathematical apparatus of Boolean functions used today to estimate the cryptographic quality of S-boxes, a cryptanalyst can apply the mathematical apparatus of functions of many-valued logic, which makes relevant the task of researching and comparing the cryptographic quality of S-boxes of modern cryptographic algorithms, represented by functions of many-valued logic. This paper presents a research and comparative analysis of nonlinear transformations of the cryptographic algorithms AES, Kalyna, BelT, and Kuznechik when represented by functions of many-valued logic. It was found that only the nonlinear transformation of the BelT cryptographic algorithm is characterized by growth when represented by many-valued logic functions, while the Kalyna cryptographic algorithm demonstrates the greatest decrease in nonlinearity when represented by 16-functions among the cryptographic algorithms researched. The results obtained in the paper indicate a significant unused reserve of cryptographic quality, which can be used in the design of new cryptographic algorithms and their structural elements.

Ultra-Low Energy CNFET-Based Ternary Combinational Circuits Designs

The embedded systems, IoT (Internet of Things) devices, and portable electronic devices spread very quickly recently. Most of them depend on batteries to operate. The target of this work is to decrease energy consumption by (1) using Multiple-valued logic (MVL) that shows notable enhancements regarding energy consumption over binary circuits and (2) using carbon nanotube field-effect transistors (CNFET) that show better performance than CMOS. This work proposes ternary combinational circuits using 32 nm CNFET: Ternary Half Adder (THA) with 36 transistors and Ternary Multiplier (TMUL) with 23 transistors. To reduce energy consumption by utilizing the unary operator of the ternary system and employing two voltage supplies ( $V_{dd}$ and $V_{dd}$ /2). The result of extensive HSPICE simulations regarding PVT (Process, Voltage, and Temperatures) variations and Noise Immunity Curve (NIC) show the improvements of the proposed designs up to 25% in transistors count and up to 98% in energy consumption reductions. Further, increasing the robustness of process variations and the noise tolerance compared to recent similar designs.

Novel Circuit Model of Multi-walled CNT Bundle Interconnects Using Multi-valued Ternary Logic

This research paper presents a novel circuit modeling and analysis of ternary logic for MWCNT bundle interconnects with active shielding under the influence of temperature variations. The far end crosstalk-induced noise and propagation delay of MWCNT bundle interconnects has been analyzed with and without the effect of shielding. A standard ternary inverter (STI) driver model is used to obtain the ternary logic at output. The temperature-dependent analysis is also carried out at different temperatures such as 300, 400 and 500 K. The temperature-dependent comparative analysis for MWCNT bundle, SWCNT bundle and copper interconnects with and without shielding is also performed. It has been observed that MWCNT bundle with active shielding outperforms the SWCNT and Cu by 75.7% and 84.4%, respectively. Similarly, the power dissipation is substantially reduced in the case of MWCNT bundle with respect to the Cu and SWCNT interconnects. It is also reported that the noise margin is marginally stable in ternary interconnects under the influence of temperature variation.