Low-Threshold II–VI Lattice-Matched SWS-FETs for Multivalued Low-Power Logic

Abstract

The aim of this paper is to design low-threshold variation, four-state/two-bit Si/SiGe quantum-well n- and p-channel spatial wavefunction-switched field-effect transistors (SWS-FETs). This is achieved by incorporating high-k lattice-matched ZnS–ZnMgS gate dielectric layers resulting in low interface charge. Quantum simulations show switching of electron wavefunction from the lower to the upper Si quantum well in the n-channel as the gate voltage is increased. In the p-channel case, the hole wavefunction switches from the upper to the lower SiGe quantum well. The novelty is in the use of high-mobility metal-oxide-semiconductor (MOS)-gate modulation-doped (MOD) SWS-FETs. The low-threshold lattice-matched gate insulator SWS-FETs are scalable to sub-7 nm and are compatible with quantum-dot nonvolatile random-access memories (QD-NVRAMs). In terms of multivalued logic (MVL) gates, our circuit simulations using the Berkeley Short-channel IGFET Model (BSIM)-based analog behavioral model (ABM) have shown two-bit/four-state output–input transfer characteristics in SWS-complementary metal oxide semiconductor (CMOS) inverters having two Si/SiGe quantum-well channels. In addition, two-bit static random-access memories (SRAMs) are designed, resulting in significantly reduced FET count and power dissipation. Finally, integration of multivalued SWS-CMOS logic, multibit QD-NVRAM cells, and SWS-based SRAMs and registers is presented.