Multiple-valued Logic Research Articles

Ternary Logic Circuit Based on Negative Capacitance Field-Effect Transistors and Its Variation Immunity

A multivalued logic (MVL) device can achieve greater data density with a smaller footprint than a traditional binary logic device. In this study, a ternary logic inverter based on negative capacitance FETs (NCFETs) without additional footprints has been realized. By enhancing the amplification in surface potential owing to the utilization of the negative capacitance, the third intermediate state can be successfully obtained at ${V}_{\text {DD}}$ /2 in the conventional binary CMOS inverter. The third intermediate state arises due to no-saturation effect of drain current, and the noise margin of the third intermediate state (NM $_{M}$ ) can be optimized by changing ferroelectric thickness or annealing temperature of ferroelectric material. The influence of remnant polarization ( ${P}_{r}$ ) and coercive electric ( ${E}_{C}$ ) variation on the ternary logic inverter was investigated based on experimental data. Moreover, a ternary logic 8T SRAM with transmission gate logic (TGL) was proposed, and the results show that the proposed 8T SRAM cell exhibits nondestructive read and reliable write operations for all three states.

El papel de Frege en la historia de la lógica

While Kant's claim has been discredited — namely that logic had, by his time, neither progressed nor regressed ever since Aristotle — both the exact reason while he was wrong and the partial core of truth his assertion contained ought to be elucidated. Aristotle's was a logic of terms that ignored the calculus of statements, cultivated instead by the Stoic logicians and later Scholastics. However a unified — yet unsuccessful — logical account of terms and propositions was attempted by Leibniz. It was an anticipation of modern combinatory logic. Leibniz's successors took over his reduction of logic to a certain mathematical calculus. Boole asserted that all logical truths were algebraic equations. Nevertheless, existential statements showed themselves unamenable to his approach. It was Frege who really made a giant step forward by resorting to variables and inventing the quantifier, thanks to his theory of objects and functions. Thus, Aristotle's logic was at last somehaw overcome. Not quite, though, since both Aristotle's and Frege's accounts share common assumptions, which have been put to rest by nonclassical logics such as combinatory and many-valued logics.

Development of Data Quality Federation for Adaptive Product Search Engine Using Big Data and Fuzzy Logic Algorithms

The rapid growth in data volumes and the need to integrate data from various heterogeneous resources bring to the fore the test of making the efficient detection of the duplicate copy of records in databases. Various ways have been proposed in recent days to address the problem; however each technique has one or more flaws that prohibit it from being successfully implemented. For this task, we offer an online machine learning method that incrementally learns a composite similarity function based on a linear combination of basic functions. The proposed work suggests an approach to improve the accuracy of the duplicate record detection process which when used in combination with two other concepts of text similarity and edit distance leads to a well filtered data. This paper advocates to usage of X - Query extension functions for XML data cleaning application scenarios, and detail the implementation on top of an existing X-Query engine. The quantitative measures of common elements in medical records are considered in this article, and fuzzy logic is used to link to language notions. Duplication Detection and Incompleteness Resolution (DDIR) approach has been proposed to improve the quality of the end users’ data. Record Linkage and Weighted Component Similarity Summing (WCSS) approach are used to detect and remove the duplicate records. The fuzzy logic framework is a powerful tool for dealing with linkage issues. The described multiple valued logic method could be used to solve similar problems in different databases. The normalized URLs are tokenized and pattern tree is constructed.

Encoding many-valued logic in $\lambda$-calculus

We will extend the well-known Church encoding of Boolean logic into $\lambda$-calculus to an encoding of McCarthy's $3$-valued logic into a suitable infinitary extension of $\lambda$-calculus that identifies all unsolvables by $\bot$, where $\bot$ is a fresh constant. This encoding refines to $n$-valued logic for $n\in\{4,5\}$. Such encodings also exist for Church's original $\lambda\mathbf{I}$-calculus. By way of motivation we consider Russell's paradox, exploiting the fact that the same encoding allows us also to calculate truth values of infinite closed propositions in this infinitary setting.

On the action of the implicative closure operator on the set of partial functions of the multivalued logic

AbstractOn the setPk∗$\begin{array}{} \displaystyle P_k^* \end{array}$of partial functions of thek-valued logic, we consider the implicative closure operator, which is the extension of the parametric closure operator via the logical implication. It is proved that, for anyk⩾ 2, the number of implicative closed classes inPk∗$\begin{array}{} \displaystyle P_k^* \end{array}$is finite. For anyk⩾ 2, inPk∗$\begin{array}{} \displaystyle P_k^* \end{array}$two series of implicative closed classes are defined. We show that these two series exhaust all implicative precomplete classes. We also identify all 8 atoms of the lattice of implicative closed classes inP3∗$\begin{array}{} \displaystyle P_3^* \end{array}$.

Design of unbalanced ternary counters using shifting literals based D-Flip-Flops in carbon nanotube technology

Digital computation using multi-valued logic decreases the requirement of interconnections which leads to a reduction in the power consumption, energy consumption and chip area in digital system design. Among various sequential logic elements, a counter is the main block that is repeatedly used for counting purposes in several processor applications. This work presents the methodology to design asynchronous and synchronous counter designs using three valued logic. The circuit implementation includes shifting operators for the D-flip-flop and counter realization in carbon nanotube technology. To realize optimized shifting circuits efficient voltage divider topology is employed by exploiting the most appropriate on-state current capability of active P-type and N-type transistors. The unique characteristic of carbon nanotube field-effect transistors (CNTFETs) to control the threshold voltage of the device by adjusting the CNT diameter favors their suitability for ternary design implementation. Thereafter, for the performance assessment of the proposed designs, simulations are conducted using the 32 nm CNTFET model using the Synopsys HSPICE simulator. Simulation results confirm the reduction in power consumption and Power delay product(PDP) of 51% and 69% for 3-bit asynchronous counter and 46% and 47% respectively for 2-bit synchronous counter design. Also, the proposed counter design shows the satisfactory operation and works reliably when simulated under different test conditions of temperature, voltage, and process variations.

Multi-State Heterojunction Transistors Based on Field-Effect Tunneling-Transport Transitions.

A monolithic ternary logic transistor based on a vertically stacked double n-type semiconductor heterostructure is presented. Incorporation of the organic heterostructure into the conventional metal-oxide-semiconductor field-effect transistor (MOSFET) architecture induces the generation of stable multiple logic states in the device; these states can be further optimized to be equiprobable and distinctive, which are the most desirable and requisite properties for multivalued logic devices. A systematic investigation reveals that the electrical properties of the device are governed by not only the conventional field-effect charge transport but also the field-effect charge tunneling at the heterointerfaces, and thus, an intermediate state can be finely tuned by independently controlling the transition between the onsets of these two mechanisms. The achieved device performance agrees with the results of a numerical simulation based on a pseudo-metal-insulator-metal model; the obtained findings therefore provide rational criteria for material selection in a simple energetic perspective. The operation of various ternary logic circuits based on the optimized multistate heterojunction transistors, including the NMIN and NMAX gates, is also demonstrated.

(Invited) Simulation-Driven Optimization of Unconventional Digital Logic Devices

Organic thin-film transistor (OTFT) based electronics has been under extensive investigation over the last three decades. Dramatic improvements have been made during this time in terms of basic device performance and stability, yet a formidable challenge remains as to how to disentangle highly complex interplays between the materials properties, device layouts, and final circuit topologies, knowing that there are simply too may possible choices for synthetically diverse, solution-processable organic electronics. In this presentation, we highlight some of our latest researches on robust simulation-based design and realization of novel organic semiconductor logic systems. We first demonstrate the possibility of guided data-level matching at the organic lateral heterojunction ternary inverters that utilize a charge anti-ambipolarity. Here, it is found that controlling the energetic diffusion barrier and minority carrier mobility is the key to obtain the evenly distributed logic values. We then switch the topic to the recently reported 3-D complementary inverter circuits where the p-type and n-type transistors are vertically integrated with a reduced circuit footprint. We focus on the critical effects of the charge injection barriers into the unintentionally doped organic semiconductors, and reveal that the systematic contact efficiency variation leads to a largely improved signal amplification gain, as well as un unusual development of the multi-valued logic behaviors up to the quaternary level. Such results clearly demonstrate that physically-based device simulation has a strong capability of correlating various influential parameters at relevant focus levels, thus paving the way toward a totally predictive engineering paradigm of new materials-based electronics platforms.

Calculi for Many-Valued Logics

We present a number of equivalent calculi for many-valued logics and prove soundness and strong completeness theorems. The calculi are obtained from the truth tables of the logic under consideration in a straightforward manner and there is a natural duality among these calculi. We also prove the cut elimination theorems for the sequent-like systems.

On the Methods of Constructing Hilbert-type Axiom Systems for Finite-valued Propositional Logics of Łukasiewicz

The article explores the following question: which among the most often examined in the literature method of constructing Hilbert-type axiom systems for finite-valued propositional logics of Łukasiewicz – the Rosser-Turquette method, the Tuziak method or the Grigolia system of axiom schemata – is in fact applicable in the researches on many-valued logics? Although the method offered by Rosser and Turquette is considered to be a solution of the problem of axiomatizability of finite-valued logics of Łukasiewicz, it has a serious limitation in producing adequate axiom systems. If the Rosser-Turquette axiom schemata are expressed just in terms of the standard propositional connectives which are definable in terms of the propositional connectives of Łukasiewicz’s logics, then every Rosser-Turquette axiom system for a Łukasiewicz’s logic is semantically incomplete. The article also examines the Tuziak axiom systems that actually axiomatize Łukasiewicz’s finite-valued logics and can be applied in the logical researches. The article compares the Tuziak axiom systems with the Grigolia set of axiom schemata, and it demonstrates that since a crucial in the Grigolia method definition of connectives is in fact invalid in Łukasiewicz’s logics, the Grigolia method does not provide sound axiom systems for Łukasiewicz’s logics.

High-Performance Spintronic Nonvolatile Ternary Flip-Flop and Universal Shift Register

Multiple-valued logic (MVL) shows considerable advantages over binary logic in certain applications because of the increased informational content of its signals, and hence reduction in interconnects. Flip-flops (FFs) are the basic elements of many systems and are widely used in microprocessors due to their high performance. This article presents two spintronic ternary retention FFs, and a nonvolatile universal ternary shift register (NUTSR) based on gate-all-around carbon nanotube field-effect transistors (GAA-CNTFETs) and nonvolatile magnetic tunnel junction (MTJ). In the proposed input-aware ternary retention FF circuit, power consumption is significantly reduced by adding a magnitude comparator (MC) circuit and preventing duplicate data transfer to MTJs. Simulation results indicate that our design offers at least 22%, 40%, and 15% reductions in power consumption, backup time, and restore energy, respectively. Moreover, it eliminates the risk of data loss in the event of a sudden power outage.

Evolutionary Game and Computer Data Optimization Control for Multi-Valued Logical Dynamic Systems

Evolutionary game theory specifically refers to the fact that today we no longer regard the traditional human model as a super rational player, but ascribe the outcome of human beings reaching the game balance to the fact that human beings seek the right method from the wrong through continuous trial and error. In the traditional control theory and the modern control theory, it is very difficult to establish the model for some systems which are described and summarized by the laws of physics or mathematics, and which have many influencing factors and are coupled with each other. With the continuous progress of science and technology, the application of computer data control system in many fields is more and more extensive, and based on the continuous advancement of modernization, the dependence on computer data control system is also constantly improving. Optimizing the computer data control system can not only greatly save time, but also improve the working efficiency of the group, thus increasing the benefits of the enterprise. In this paper, from the optimization control of computer data system as the analysis goal, through the study of evolutionary game theory and the analysis of multi-valued logic dynamic system, and then combined with the optimization control of computer data, this problem is discussed and analyzed from multiple aspects.

Design and Analysis of Multiplier Using High Speed Adders

In all digital signal processing (DSP) applications like FFT, digital filters the main problem faced by processor is its propagation delay. Every high speed signal processing is depends on multiplier circuits. Multiplier performance is directly influenced by the adder design. In this paper, we design low power and high speed carry look ahead (CLA) adder for multiplier circuit by using multi value logic (MVL) based on quaternary signed digits (QSD). The ability of multi value logic (MVL) circuits to achieve more information density and high operating speed when compared to that of existing binary circuits is highly impressive. MVL circuits have attracted important attention for the design of digital systems. Based on quaternary signed digits, the carry look ahead adder is designed, implemented in multiplier circuit and simulated by using cadence virtuoso design suite by 180nF technology.

Modified Septenary System-based logic gates using SLM and savart plate

Optical computing is a significant improvement over conventional electronic circuits due to much higher computing speeds and better data handling capabilities. A multivalued logic (MVL) system incorporates more than two logical states to enable higher data density, reduce or eliminate ripple-through carries in arithmetic operations. Optical multivalued logic may be one of the best solutions in modern computational system to resolve the recent problems associated with the existing one. The singed-bit states in a multivalued logic system also permits simplified carry or borrow free operations. In this paper an optical multivalued logic system with signed-bit is introduced, called Modified Septenary System (MSS). The seven logical states of the system are introduced and different arithmetic and logical operations are also implemented accordingly. The different logic gates of this system are designed and realized with SLM and savart plate using Optical Tree Architectures (OTA).

A Talmudic norms approach to many-valued logic

AbstractIn three-valued logic, the third truth-value is often interpreted as undefined. However, the value of a logical term may be well defined if its ‘history’ is taken into account. Following this approach, the analogy to the Sorites paradox meets the eye, which in turn has recently been addressed by means of a ‘Talmudic Norms’ approach. This paper thus lays bare a religious contribution to the field of many-valued logic and implements a simplified dynamic model for the theory of Talmudic mixtures—and, thus, for the outlined Sorites logic—using standard AI search and planning techniques.

Tense De Morgan S4-algebras

In [Tense operators on De Morgan algebras, Log. J. IGPL 22(2) (2014) 255–267], Figallo and Pelaitay introduced the notion of tense operators on De Morgan algebras. Also, other notions of tense operators on De Morgan algebras were given by Chajda and Paseka in [De Morgan algebras with tense operators, J. Mult.-Valued Logic Soft Comput. 1 (2017) 29–45; The Poset-based logics for the De Morgan negation and set representation of partial dynamic De Morgan algebras, J. Mult.-Valued Logic Soft Comput. 31(3) (2018) 213–237; Set representation of partial dynamic De Morgan algebras, in 2016 IEEE 46th Int. Symp. Multiple-Valued Logic (IEEE Computer Society, 2016), pp. 119–124]. In this paper, we introduce a new notion of tense operators on De Morgan algebras and define the class of tense De Morgan [Formula: see text]-algebras. The main purpose of this paper is to give a discrete duality for tense De Morgan [Formula: see text]-algebras. To do this, we will extend the discrete duality given in [W. Dzik, E. Orłowska and C. van Alten, Relational Representation Theorems for Lattices with Negations: A Survey, Lecture Notes in Computer Science (2006), pp. 245–266], for De Morgan algebras.

Truth Pluralism and Many-Valued Logic: Lesson from Suszko’s Thesis

AbstractAccording to truth pluralism, sentences from different areas of discourse can be true in different ways. This view has been challenged to make sense of logical validity, understood as necessary truth preservation, when inferences involving different areas are considered. To solve this problem, a natural temptation is that of replicating the standard practice in many-valued logic by appealing to the notion of designated values. Such a simple approach, however, is usually considered a non-starter for strong versions of truth pluralism, since designation seems to embody nothing but a notion of generic truth. In this paper, I explore the analogy with many-valued logic by comparing the problem of mixed inferences with Suszko’s thesis, and argue that the strong pluralist has room to resist the commitment to a generic property of truth by undermining the semantic significance of Suszko’s reduction.

Multivalued Logic Gates: Recent Advances on Multivalued Logic Gates: A Materials Perspective (Adv. Sci. 8/2021)

Emerging materials and device architectures for the realization of multivalued logic operations are investigated. In article number 2004216, Sae Byeok Jo, Joohoon Kang, and Jeong Ho Cho provide an overview of the recent advancements in multivalued logic gates from a materials perspective, in which a paradigm shift toward a new era of hyper Moore's law is manifested through the development of area- and energy-efficient architectures.

Design of odd-even multiplexer for all-edges-triggered flip-flops

ABSTRACT Multivalued flip-flops play an important role in multivalued circuits, and their clocks can also be multivalued. According to the switching rule of multivalued clocks and the operating principle of latches, this study proposes an effective method of handling multivalued clocks and a novel odd-even multiplexer for all-edges-triggered flip-flop (AETFF) based on multivalued clocks. The AETFFs structure consisting of odd-even multiplexers i.e. the oeAETFF structure not only senses every edge of multivalued clocks and functions properly, but also is much simpler and more efficient than the previous one. According to the oeAETFF structure, binary or multivalued AETFFs based on arbitrary radices clocks can be easily obtained with a simpler circuit. The oeAETFF structure not only can be implemented by CMOS technology, but also could be used as a helpful reference to guide the flip-flops design with the next-generation devices suitable for multivalued logic. At last, a CMOS quaternary oeAETFF based on quaternary clock is implemented as an instance of the oeAETFF structure. It is validated to function properly with a simpler circuit and higher efficiency by simulation and comparison.

Demonstration of programmable ternary graphene field-effect transistor using ferroelectric polymer doping

Ternary logic technology facilitates simplifying logic circuits and reducing power consumption. In this study, a universal ternary device that can be programmed into an n-type and p-type ternary device is demonstrated using a graphene field-effect transistor with a P(VDF-TrFE)/graphene stack channel. The feasibility of a standard ternary inverter function is demonstrated by complementary ternary GFETs, which have discretely programmed n-doped and p-doped graphene channels with different channel widths. Even though the performance of the ternary inverter should be improved further, the concept of the programmable ternary logic, based on channel width modulation and ferroelectric doping, is useful for future experimental studies on the multi-valued logic architecture. • Complementary ternary graphene field-effect transistors using ferroelectric polymer doping effects were demonstrated. • Modulation of the channel widths of series-connected GFETs has been demonstrated. • Semi-empirical graphene logic device model confirms complementary ternary logic system viability.