Carbon Nanotube Field Effect Transistor (CNTFET) and Resistive Random Access Memory (RRAM) Based Ternary Combinational Logic Circuits

Furqan Zahoor,Farooq Ahmad Khanday,Illani Mohd Nawi,Chia Yee Ooi,Fawnizu Azmadi Hussin,Mohamad Radzi Ahmad,Fakhrul Zaman Rokhani

doi:10.3390/electronics10010079

Abstract

The capability of multiple valued logic (MVL) circuits to achieve higher storage density when compared to that of existing binary circuits is highly impressive. Recently, MVL circuits have attracted significant attention for the design of digital systems. Carbon nanotube field effect transistors (CNTFETs) have shown great promise for design of MVL based circuits, due to the fact that the scalable threshold voltage of CNTFETs can be utilized easily for the multiple voltage designs. In addition, resistive random access memory (RRAM) is also a feasible option for the design of MVL circuits, owing to its multilevel cell capability that enables the storage of multiple resistance states within a single cell. In this manuscript, a design approach for ternary combinational logic circuits while using CNTFETs and RRAM is presented. The designs of ternary half adder, ternary half subtractor, ternary full adder, and ternary full subtractor are evaluated while using Synopsis HSPICE simulation software with standard 32 nm CNTFET technology under different operating conditions, including different supply voltages, output load variation, and different operating temperatures. Finally, the proposed designs are compared with the state-of-the-art ternary designs. Based on the obtained simulation results, the proposed designs show a significant reduction in the transistor count, decreased cell area, and lower power consumption. In addition, due to the participation of RRAM, the proposed designs have advantages in terms of non-volatility.

Highlights

IntroductionInterconnects are the main source of power dissipation within a VLSI chip and they comprises 70% of total on-chip capacitance [1]
To get over the limitations of binary logic, a logic system having more than two values that are associated with the logic levels, which is commonly referred to as the multiple valued logic (MVL), can be used for implementing digital system design
Carbon nanotube field effect transistors (CNTFETs) 32nm of computing systems utilizing ternary logic designs has come to the fore in recent years, owing to the significant research that has focussed on emerging technologies

Summary

Introduction

Interconnects are the main source of power dissipation within a VLSI chip and they comprises 70% of total on-chip capacitance [1] In integrated circuits, these interconnects occupy additional area, thereby causing several signal integrity issues such as noise and delay jitters. Owing to the fact that the MVL utilizes more than two logic levels, MVL-based systems provide the transmission of a greater amount of information when compared to binary logic systems over a single wire, which helps to significantly reduce the on-chip and off-chip interconnections. The designs utilizing MVL for its implementation offer advantages in terms of increased information density, reduced chip area, and improved computational capability of the integrated circuits. Ternary logic is of considerable interest, due to its ease of implementation and energy efficiency because of the reduced complexity of interconnects and chip area [5]

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