Multi-bit Upsets Research Articles

A Hierarchical Priority Based Multi-Bit Error Tolerant Design for FPGA Configuration Memory

The reconfigurability of a field-programmable gate array (FPGA), which is utilized in many applications, permits changes to be made to an existing design. In hostile environments such as space, where radiation and ionizing particles increase the risk for failure and human maintenance is either impossible or time-consuming, this reconfigurable capability becomes even more important. Single event upsets (SEUs) and multi-bit upsets (MBUs) on configuration memory can cause soft errors and circuit malfunctions in SRAM-based field programmable gate arrays (FPGAs). The ever-increasing quantity of configuration bits in contemporary FPGAs makes it more difficult for traditional scrubbing to identify faults in a timely manner, leading to a mismatch between scrubbing performance and MBU sensitivity.A hierarchical multi-bit error correcting method fully utilizes the MBU sensitivity at various configuration frame locations. It employs distinct techniques for varying priorities and differentiates across configuration frames with multiple priorities. They divided code words into several sections and used distinct error-correction techniques in each section. In high radiation conditions, the suggested integrated error correction technique enhances FPGA configuration memory protection by substituting memory scrubbing. The suggested approach lowers total TTD and enables priority-based asynchronous MBU detection and correction. Index Terms—FPGA,MBU,Sensitivity,Configuration memory

Two-Dimensional Protection Code for Virtual Page Information in Translation Lookaside Buffers

Severe conditions such as high-energy particle strikes may induce soft errors in on-chip memory, like cache and translation lookaside buffers (TLBs). As the key component of virtual-to-physical address translation, TLB directly affects processor performance. To protect the virtual page information stored in TLB, several studies have introduced error detection or correction codes. However, most schemes proposed for data TLB cannot support the detection of multi-bit upsets, which is reported as a serious issue in modern fault-tolerant processors due to the downscaling of CMOS process technology. In this paper, we propose a new two-dimensional protection technique, called the matrix protection tag (MaP-Tag), to provide stronger error detection and correction capability to TLB virtual page information. Our proposal reorganizes virtual page information into a matrix and employs adjacent check bits and interleaved check bits for error detection. The two-dimensional design offers one-bit error detection, burst multi-bit error detection, and even multi-bit error correction in some cases. The simulation results show that our proposal can detect almost all error patterns when injected with up to eight bit-flips. Furthermore, the technique provides a better error correction rate than conventional single error correction (SEC) codes. The reliability calculation shows that our proposal is powerful in both error detection and correction with affordable storage overhead.

Multibit Upsets of Onboard Spacecraft Electronics from a Single Cosmic Radiation Particle

Multibit Upsets of Onboard Spacecraft Electronics from a Single Cosmic Radiation Particle

Multi-bit Data Flow Error Detection Method Based on SDC Vulnerability Analysis

One of the most difficult data flow errors to detect caused by single-event upsets in space radiation is the Silent Data Corruption (SDC). To solve the problem of multi-bit upsets causing program SDC, an instruction multi-bit SDC vulnerability prediction model based on one-class support vector machine classification is built using SDC vulnerability analysis, which has more accurate vulnerability instruction identification capabilities. By hardening the program with selective instruction redundancy, we propose a multi-bit data flow error detection method for detecting SDC error (SDCVA-OCSVM), aiming to protect the data in the memory or register used by the program. We have also verified the effectiveness of the method through comparative experiments. The method has been verified to have a higher error detection rate and lower code size and time overhead.

HARDeNN: Hardware-assisted attack-resilient deep neural network architectures

We propose HARDeNN, a low-overhead end-to-end inference accelerator methodology to armor the underlying pre-trained neural network architecture against black-box non-input adversarial attacks. In order to find the most vulnerable neural network architectures parameters, a hardware-assisted fault injection tool and a statistical stress model have been proposed to synergy uniform fault assessment across layers and targeted in-layer fault assessment to realize a holistic, rigorous fault evaluation in NN topologies susceptible to non-input adversarial black-box attacks. The key observation from the assessment shows that the weights and activation functions are the most vulnerable neural network parameters that are susceptible to both single-bit and multiple-bit flip attacks. Concerning the aforementioned parameters, a multi-objective design space exploration is conducted to find a superior design under different resource constraints. The error-resiliency magnitude offered by HARDeNN can be adjusted based on the given boundaries. The experimental results show that HARDeNN methodology enhances the error-resiliency magnitude of cnvW1A1 by 17.19% and 96.15% for 100 multi-bit upsets that target weight and activation layers, respectively, during CIFAR-10 classification.© 2017 Elsevier Inc. All rights reserved.

Experimental Study on the Space Electrostatic Discharge Effect and the Single Event Effect of SRAM Devices for Satellites

Space Electrostatic Discharge Effect (SESD) and Single Event Effect (SEE) are two major space environmental factors that cause spacecraft failure. Previous studies have established that both can lead to soft errors such as upset of memory cells. An ESD generator and a pulsed laser experimental facility were used to test a low-power asynchronous timing monolithic SRAM. The characteristics of soft error number, single/multi-bit upsets, and supply current values were compared for similarities and differences. The test revealed that SEE-induced soft errors were mainly single-bit upsets (SBU), whereas SESD-induced soft errors were predominantly multi-bit upsets (MBU). Additionally, when soft errors occur in the circuits, the current of the power supply drops, which enables the device to be evaluated by monitoring the current value. This study provides experimental support for distinguishing device errors caused by these two effects, as well as references for further accurate identification of in-orbit faults and corresponding protection design.

MLFTCache: Multilevel Fault Tolerance Scheme for Write-Back L2 Cache Under Irradiation

Cache is prone to soft errors under irradiation, and the incidence rate of multi-bit soft errors in cache memory are becoming larger for modern embedded systems. To improve the cache reliability, we propose a multi-level fault tolerance scheme for write-back L2 cache (MLFTCache). In the workflow of MLFTCache, data bits of cache clean line and dirty line are processed separately. For clean line data bits, 2-way interleaved parity is adopted, and the error is detected and recovered from the next level of memory. For dirty line data bits, the processing is further divided into two layers. The first layer adopts single error correction double error detection (SECDED) code, and the second layer uses multi-bit low redundancy error control with parity sharing (MLREPS) code to detect and correct errors. To reduce the overhead and improve the efficiency of fault tolerance on dirty lines, we adopt two write-back mechanisms. Early write-back mechanism is used to reduce the occurrence of temporal multi-bit soft errors, and emergency write-back mechanism is adopted to deal with the soft error after it is detected. The alpha radiation experiments of Xilinx Zynq-7010 SoC show that cache is prone to multi-bit upsets and the MLFTCache is also dedicated to solving the problem of multi-bit upsets. The cache fault injection and tolerance experiments show that the fault tolerance rate of the MLFTCache proposed in this paper exceeds 90%, while the benchmark schemes are less than 50%. Besides, MLFTCache also has a good performance on dual-core CPU, and its fault tolerance rate on average is 91.34%.

Design and Evaluation of Radiation-Hardened Standard Cell Flip-Flops

Use of a standard non-rad-hard digital cell library in the rad-hard design can be a cost-effective solution for space applications. In this paper we demonstrate how a standard non-rad-hard flip-flop, as one of the most vulnerable digital cells, can be converted into a rad-hard flip-flop without modifying its internal structure. We present five variants of a Triple Modular Redundancy (TMR) flip-flop: baseline TMR flip-flop, latch-based TMR flip-flop, True-Single Phase Clock (TSPC) TMR flip-flop, scannable TMR flip-flop and self-correcting TMR flip-flop. For all variants, the multi-bit upsets have been addressed by applying special placement constraints, while the Single Event Transient (SET) mitigation was achieved through the usage of customized SET filters and selection of optimal inverter sizes for the clock and reset trees. The proposed flip-flop variants feature differing performance, thus enabling to choose the optimal solution for every sensitive node in the circuit, according to the predefined design constraints. Several flip-flop designs have been validated on IHP’s 130nm BiCMOS process, by irradiation of custom-designed shift registers. It has been shown that the proposed TMR flip-flops are robust to soft errors with a threshold Linear Energy Transfer (LET) from ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$32.4\, \frac { {\mathrm { \text {M} \text {eV} }}\cdot {\mathrm { \text {c} \text {m} }}^{2}}{ {\mathrm { \text {m} \text {g} }}}$ </tex-math></inline-formula> ) to ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$62.5\, \frac { {\mathrm { \text {M} \text {eV} }}\cdot {\mathrm { \text {c} \text {m} }}^{2}}{ {\mathrm { \text {m} \text {g} }}}$ </tex-math></inline-formula> ), depending on the variant.

Neutron Radiation Testing of a TMR VexRiscv Soft Processor on SRAM-Based FPGAs

Soft processors are often used within field-programmable gate array (FPGA) designs in radiation hazardous environments. These systems are susceptible to single-event upsets (SEUs) that can corrupt both the hardware configuration and software implementation. Mitigation of these SEUs can be accomplished by applying triple modular redundancy (TMR) techniques to the processor. This article presents fault injection and neutron radiation results of a Linux-capable TMR VexRiscv processor. The TMR processor achieved a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10\times $ </tex-math></inline-formula> improvement in SEU-induced mean fluence to failure with a cost of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4\times $ </tex-math></inline-formula> resource utilization. To further understand the TMR system failures, additional post-radiation fault injection was performed with targets generated from the radiation data. This analysis showed that not all the failures were due to single-bit upsets, but potentially caused by multibit upsets, nontriplicated IO, and unmonitored nonconfiguration RAM (CRAM) SEUs.

Clustered Error Resilient SRAM-Based Reconfigurable Computing Platform

In the present age of high-density integrated circuits, radiation-induced adjacent multibit upsets (AMBUs) or clustered errors are very prominent in the configuration memory of static-random-access-memory-based field-programmable gate array (FPGA) devices. Radiated particles with high energy and low momentum may damage a group of adjacent logic cells and switches in reconfigurable devices, which can lead to clustered errors. Commonly used error mitigation techniques in the FPGA either have large overheads, complex decoding circuitry, or are not very efficient to correct AMBUs. Hence, efficient multibit error-correcting codes with low redundancy are of utmost need to mitigate the effect of AMBUs. Configuration data of the FPGAs are composed of a number of configuration frames (CFs), and there is a high probability that multiple physically adjacent CFs may be affected by clustered error. Hence, interleaving among CFs is quite advantageous for mitigation of clustered errors in the configuration memory of the FPGA. In this article, we have proposed a simple and efficient error mitigation model combining Hamming product code (HPC) with frame interleaving and selective bit placement, termed as “HPCFISBP” to correct AMBUs in the configuration memory of the FPGA without any modification in its basic architecture. The HPCFISBP provides better bit error rate performance nearly by 20 and 10 dB compared to Hamming code and HPC, respectively. The enhanced performance of the HPCFISBP has also been established through comparison with the state-of-the-art techniques in terms of error correction coverage, error correction time, redundancy, and residual error.

Latency optimized clustered error mitigation for multi-level flash memory using product code

Soft errors due to radiation-induced multi-bit upsets (MBUs) are very prominent in the present flash memories built with ultra large scale VLSI technology. Use of multi-level cells in flash memories increase the chance of adjacent MBUs or clustered error. Single bit error detection and correction (EDAC) codes are not enough to mitigate the effect of clustered error due to their small error correction capability. On the other hand, commonly used multi-bit EDAC codes have large overhead, complex decoding circuitry, high error correction latency and are unable to correct large number adjacent erroneous bits. In this paper, we have proposed a product code coined as linear shortened block code based product code (LSBCPC) for mitigation of clustered error in the flash memory devices. LSBCPC utilizes latency optimized scalable shortened block code as the component code and can correct higher number of adjacent erroneous bits in memory devices compared to the other state of the art solutions. The proposed LSBCPC promises better error correction coverage with 28%, 14%, and 13% reduction in terms of redundant bits, 13%, 11%, and 10% reduction in terms of area and 24%, 26%,and 22% reduction in terms of latency in 16 × 16, 32 × 32 and 64 × 64 memory devices respectively compared to the highly cited research work. The performance of the proposed method is validated in terms of redundant bits, error correction coverage, mean error to failure, area consumption, power utilization and decoding latency.

Modifying Hamming code and using the replication method to protect memory against triple soft errors

As technology scaling increases computer memory’s bit-cell density and reduces the voltage of semiconductors, the number of soft errors due to radiation induced single event upsets (SEU) and multi-bit upsets (MBU) also increases. To address this, error-correcting codes (ECC) can be used to detect and correct soft errors, while x-modular-redundancy improves fault tolerance. This paper presents a technique that provides high error-correction performance, high speed, and low complexity. The proposed technique ensures that only correct values get passed to the system output or are processed in spite of the presence of up to three-bit errors. The Hamming code is modified in order to provide a high probability of MBU detection. In addition, the paper describes the new technique and associated analysis scheme for its implementation. The new technique has been simulated, evaluated, and compared to error correction codes with similar decoding complexity to better understand the overheads required, the gained capabilities to protect data against three-bit errors, and to reduce the misdetection probability and false-detection probability of four-bit errors.

An energy efficient and low overhead fault mitigation technique for internet of thing edge devices reliable on‐chip communication

SummarySoft errors in network‐on‐chip (NoC) such as single bit upsets and multibit upsets cause hazardous effects such as congestion, deadlock, livelock, and corruption of data. Error‐correcting codes (ECCs) are the best choices to handle these soft errors in links and memory buffers of NoC, which is the need of all modern systems, including internet of thing (IoT) edge devices. Many of these ECCs cannot correct both random and burst errors. Specific codes possess the correction and detection capability at the cost of an increase in area, latency, and energy. In this article, a coding technique is proposed by using a single error correction double error detection‐triple adjacent error correction‐six adjacent error detection (SEC‐DED‐TAEC‐6AED) (24,16) I5, that provides both random and burst error fault tolerance for NoC. The proposed technique decreases the area, energy, and latency cost of the whole NoC. It also reduces the area overhead to 173.41% and 117.91% compare to joint crosstalk avoidance multiple error correction (JCAMEC) and joint crosstalk multiple error correction (JMEC), respectively. Besides, the delay overhead of the proposed technique reduces to 4.2% and 91.97% compared with JCAMEC and JMEC, respectively. The simulation results show that the proposed code possesses an enhanced ability of error correction and detection with 3.5 times less redundant bits and a 30% fast code rate compared with JMEC and JCAMEC. Hence, the proposed scheme can effectively be used for detecting and correcting single and multiple bit errors for on‐chip communication.

Single Event Effect Testing With Ultrahigh Energy Heavy Ion Beams

Single event effect (SEE) testing with ultrahigh energy (UHE) heavy ions, such as the beams provided at CERN, presents advantages related to their long ranges with a constant linear energy transfer value. In the present work, the possibility to test components in parallel is being examined, and results from the CERN 2018 UHE Pb test campaigns are studied. Furthermore, the generation of multibit upsets by the UHE Pb ions is evaluated, and the contribution of possible fragments to the SEE measurements is discussed.

SEE Sensitivity Evaluation for Commercial 16 nm SRAM-FPGA

Radiation effects can induce severe and diverse soft errors in digital circuits and systems. A Xilinx commercial 16 nm FinFET static random-access memory (SRAM)-based field-programmable gate array (FPGA) was selected to evaluate the radiation sensitivity and promote the space application of FinFET ultra large-scale integrated circuits (ULSI). Picosecond pulsed laser and high energy heavy ions were employed for irradiation. Before the tests, SRAM-based configure RAMs (CRAMs) were initialized and configured. The 100% embedded block RAMs (BRAMs) were utilized based on the Vivado implementation of the compiled hardware description language. No hard error was observed in both the laser and heavy-ion test. The thresholds for laser-induced single event upset (SEU) were ~3.5 nJ, and the SEU cross-sections were correlated positively to the laser’s energy. Multi-bit upsets were measured in heavy-ion and high-energy laser irradiation. Moreover, latch-up and functional interrupt phenomena were common, especially in the heavy-ion tests. The single event effect results for the 16 nm FinFET process were significant, and some radiation tolerance strategies were required in a radiation environment.

An SRAM-Based Radiation Monitor With Dynamic Voltage Control in 0.18-&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\mu$ &lt;/tex-math&gt; &lt;/inline-formula&gt;m CMOS Technology

This paper presents a novel radiation monitor that is based on a custom static random access memory (SRAM) application-specified integrated circuit. Its sensitivity is adjustable through its core supply voltage and the radiation monitoring is based on the upset rate that is measured during a measurement interval in the memory. The sensor has different supply voltages for the SRAM core and the interface logic to prevent incorrect digital signals during the measurement cycle. The memory was processed in a 0.18- $\mu \text{m}$ CMOS technology and was tested with heavy ions with an linear energy transfer from 1.8–60 MeV $\cdot $ cm2/mg, 24-GeV protons, and a mixed radiation field. The memory cells were also verified with a two-photon absorption laser. Furthermore, an analysis was made on single-event upsets and multibit upsets.

Modeling Application-Level Soft Error Effects for Single-Event Multi-Bit Upsets

Transient errors induced by radiations cause bit-flips in flip-flops (flip-flop soft errors). Modeling the error resilience level of a target system for flip-flop soft errors is a crucial step to achieve a cost-effective error resilience solution. This step often requires a significant amount of time and effort for a large number of fault injection simulations. As technology scales, the required effort grows in a new dimension with the increased probability of multi-bit upsets (MBUs). In this work, we present a new estimation model that predicts the resulting error resilience levels for the flip-flop MBU cases. This estimation model only requires the measured soft error effects of the single-bit upset (SBU) cases. This model uses two strategies to address how multiple bit-flips that happen simultaneously in a system affects the outcome of application execution. We evaluate the accuracy level of the MBU estimation model using actual fault injection results on two different processor cores. The two main strategies in our estimation model improve the accuracy levels by more than 7×.

A Hybrid Approach to FPGA Configuration Scrubbing

This paper describes a FPGA configuration scrubbing approach for Xilinx 7-Series FPGAs that combines the high-speed internal scrubbing available within these devices with an external scrubber. The internal scrubbing unit continuously monitors the frames of the FPGA configuration memory and corrects single-bit frame errors and is used to detect multi-bit frame errors. Multi-bit upsets are repaired by means of a secondary scrubbing mechanism that is primarily external to the FPGA fabric. This Xilinx 7-Series hybrid configuration scrubbing architecture scans 25,636,224 bits of the XC7Z020 device in several microseconds and detects upsets within 8 ms and then corrects most multi-cell upsets in under an additional 6 ms. This configuration scrubber was validated with configuration fault injection and neutron radiation testing.

Efficient dynamic priority based soft error mitigation techniques for configuration memory of FPGA hardware

Radiation-induced single bit upsets (SBUs) and multi-bit upsets (MBUs) are more prominent in Field Programmable Gate Arrays (FPGAs) due to the presence of a large number of latches in the configuration memory (CM) of FPGAs. At the same time, SBUs and MBUs in the CM can permanently or temporarily affect the hardware circuit implemented on FPGA. Hence, error mitigation and recovery techniques are necessary to protect the FPGA hardware from permanent faults arising due to such SBUs and MBUs. Different existing techniques used to mitigate the effect of soft errors in FPGA have high overhead and their implementations are also quite complex. In this paper, we have proposed efficient single bit as well as multi-bit error correcting methods to correct errors in the CM of FPGAs using simple parity equations and Erasure code. These codes are easy to implement, and the needed decoding circuits are also simple. Use of Dynamic Partial Reconfiguration (DPR) along with a simple hardware scheduling algorithm based download manager helps to perform the error correction in the CM without suspending the operations of the other hardware blocks. We propose a first of its kind methodology for novel transient fault correction using efficient error correcting codes with hardware scheduling for FPGAs. To validate the design we have tested the proposed methodology with Kintex FPGA. We have also measured different parameters like fault recovery time, power consumption, resource overhead and error correction efficiency to estimate the performance of our proposed methods.

Low latency radiation tolerant self-repair reconfigurable SRAM architecture

In this paper we present a low latency reconfigurable radiation tolerant memory architecture for mission-critical applications based on the RTSR (Radiation Tolerant Self-Repair) cell. The proposed architecture offers detection and correction during the read cycle at high frequencies. Through reconfiguration circuitry, the memory can operate in two modes, one providing soft error tolerance and another geared towards increased (×3) memory capacity. Compared to the conventional Triple Modular Redundancy, the proposed memory architecture provides radiation tolerance for single and multi-bit upsets with improved latency, area and power characteristics. An enhanced version of the RTSR-based memory architecture is also presented (RTSR+), whereby we can boost performance by embedding a small accelerator circuit. From simulation results on a layout implementation of the proposed memory architecture in a 65nm technology, with PVT variations and parasitics taken into account, the RTSR+ architecture can achieve up to 200% performance increase compared to the RTSR architecture in certain memory configurations.