Clustered Error Resilient SRAM-Based Reconfigurable Computing Platform

Abstract

In the present age of high-density integrated circuits, radiation-induced adjacent multibit upsets (AMBUs) or clustered errors are very prominent in the configuration memory of static-random-access-memory-based field-programmable gate array (FPGA) devices. Radiated particles with high energy and low momentum may damage a group of adjacent logic cells and switches in reconfigurable devices, which can lead to clustered errors. Commonly used error mitigation techniques in the FPGA either have large overheads, complex decoding circuitry, or are not very efficient to correct AMBUs. Hence, efficient multibit error-correcting codes with low redundancy are of utmost need to mitigate the effect of AMBUs. Configuration data of the FPGAs are composed of a number of configuration frames (CFs), and there is a high probability that multiple physically adjacent CFs may be affected by clustered error. Hence, interleaving among CFs is quite advantageous for mitigation of clustered errors in the configuration memory of the FPGA. In this article, we have proposed a simple and efficient error mitigation model combining Hamming product code (HPC) with frame interleaving and selective bit placement, termed as “HPCFISBP” to correct AMBUs in the configuration memory of the FPGA without any modification in its basic architecture. The HPCFISBP provides better bit error rate performance nearly by 20 and 10 dB compared to Hamming code and HPC, respectively. The enhanced performance of the HPCFISBP has also been established through comparison with the state-of-the-art techniques in terms of error correction coverage, error correction time, redundancy, and residual error.