Abstract
Transient errors induced by radiations cause bit-flips in flip-flops (flip-flop soft errors). Modeling the error resilience level of a target system for flip-flop soft errors is a crucial step to achieve a cost-effective error resilience solution. This step often requires a significant amount of time and effort for a large number of fault injection simulations. As technology scales, the required effort grows in a new dimension with the increased probability of multi-bit upsets (MBUs). In this work, we present a new estimation model that predicts the resulting error resilience levels for the flip-flop MBU cases. This estimation model only requires the measured soft error effects of the single-bit upset (SBU) cases. This model uses two strategies to address how multiple bit-flips that happen simultaneously in a system affects the outcome of application execution. We evaluate the accuracy level of the MBU estimation model using actual fault injection results on two different processor cores. The two main strategies in our estimation model improve the accuracy levels by more than 7×.
Highlights
Bit-flips caused by high-energy particle strikes are one of the leading reliability concerns in digital systems [1], [2]
The multi-bit upsets (MBUs) estimation model introduced in this work estimates the application-level effects of MBU flip-flop soft errors with high accuracy
The accuracy levels of our MBU estimation model is verified using actual fault injection results that include a wide range of applications and multiple bit-flip counts
Summary
Bit-flips caused by high-energy particle strikes (soft errors) are one of the leading reliability concerns in digital systems [1], [2]. We present a mechanism to estimate the application-level effects of flip-flop MBUs using the fault injection results that model flip-flop SBU cases only. Once we conduct fault injection runs for singlebit flips, our mechanism models the effects of multi-bit flips without requiring additional fault injection runs that inject multiple bit-flips This estimation model can reduce the efforts for soft error resilience evaluation because the resource-consuming fault injection runs can be limited to single-bit injections only. We present evaluation results through fault injection runs that model the effects of multi-bit flip-flop soft errors in processor cores. Our MBU estimation model uses two main strategies that address the application’s behavior under multiple faults and the number of bit-flips that affect the execution Since this is the first estimation model for the application-level effects of MBUs in flip-flops, we devise a baseline model that uses a simple mechanism for MBU estimation (naïve estimation model).
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