Micron CMOS Technology Research Articles

Design of a Fractional Order Low-pass Filter Using a Differential Voltage Current Conveyor

In this paper, an active implementation of a differential voltage current conveyor (DVCC) based on a low-pass filter operating in the fractional order domain is presented. The transfer function for a fractional order system is dependent on the rational approximation of sα. Different methods used for calculating the rational approximation, including Carlson, Elkhazalil, and curve fitting, are evaluated here. Finally, to validate the theoretical results, a fractional order Butterworth filter is simulated in the Pspice environment using the 0.5 micrometer CMOS technology with an R-C network-based fractional order capacitor. Additionally, using the Monte Carlo analysis, the impact of current and voltage faults on DVCC response is investigated. It has been inferred that realization with a wider bandwidth is possible.

Design and Analysis of Full Adder Using 0.6 Micron CMOS Technology

The design of a full adder involves the use of logic gates so that the design can convert 8 inputs to create a byte-wide adder and to force the carry bit to the other adder. However, the uses of multiplexers to replace the logic gates in the construction of the full adder is proven to be possible due to the function of the multiplexers to act as the digital switch in the system that provides the flow of digital information from multiple inputs into an output. This research aims to explore the possibility of implementing the multiplexers into the design of the full adder and to analyse the different possible full adder design using the multiplexers. Using the multiplexers also allows for fewer logic gates to be used in the design of the full adder, which reduces the overall area coverage of the full adder. However, adding multiplexers does not make a complete adder more efficient and may slow it down. Thus, this article compares a conventional full adder with logic gates, a full adder with two 2:1 multiplexers, and a full adder with six 2:1 multiplexers in terms of power usage, time delay of the Sum and Carry outputs, and technology (0.6 μm).

A 10 GS/s time-interleaved ADC in 0.25 micrometer CMOS technology

Abstract This paper presents design and simulation of a 4-bit 10 GS/s time interleaved ADC in 0.25 micrometer CMOS technology. The designed TI-ADC has 4 channels including 4-bit flash ADC in each channel, in which area and power efficiency are targeted. Therefore, basic standard cell logic gates are preferred. Meanwhile, the aspect ratios in the gate designs are kept as small as possible considering the speed performance. In the literature, design details of the timing control circuits have not been provided, whereas the proposed timing control process is comprehensively explained and design details of the proposed timing control process are clearly presented in this study. The proposed circuits producing consecutive pulses for timing control of the input S/H switches (ie the analog demultiplexer front-end circuitry) and the very fast digital multiplexer unit at the output are the main contributions of this study. The simulation results include +0.26/−0.22 LSB of DNL and +0.01/−0.44 LSB of INL, layout area of 0.27 mm2, and power consumption of 270 mW. The provided power consumption, DNL and INL measures are observed at 100 MHz input with 10 GS/s sampling rate.

Design of 900 Mhz AC to DC Converter Using Native Cmos Device of TSMC 0.18 Micron Technology for RF Energy Harvest Application

RF signal carries very low amount of energy and can be easily dissipated as heat loss. Threshold voltage and leakage current that are inherent in MOS transistors significantly affect the performance of an RF AC to DC converter. A device with bulk connected to its drain improves the threshold voltage and leakage current. This work designs the half-wave and full-wave AC to DC converters with devices' bulk connected to source and devices' bulk connected to drain. The designs used the native devices in TSMC 0.18 micron CMOS technology, and were simulated using transient analysis in different process corners and operating temperatures. In simulations, the RF signal was represented by a sinusoidal input of 900 MHz frequency and of 390 mV amplitude. The sizes of transistors and the number of stages, of each converter, that resulted to highest power efficiency were determined via circuit simulations. The optimal design was a four-stage half-wave AC to DC converter with devices' bulk connected to drain, which produced a DC output of 2.7 V with 37.42 % efficiency at 100 kilo ohm load.

CLARO-CMOS: a fast, low power and radiation-hard front-end ASIC for single-photon counting in 0.35 micron CMOS technology

The CLARO-CMOS is a prototype ASIC designed for fast photon counting with multi-anode photomultiplier tubes (MaPMT). The CLARO features a 5 ns peaking time, a recovery time to baseline smaller than 25 ns, and a power consumption of less than 1 mW per channel. The chip was designed in 0.35 μm CMOS technology, and was tested for radiation hardness with neutrons up to 1014 1 MeV neq/cm2, X-rays up to 40 kGy and protons up to 76 kGy. Its capability to read out single photons at high rate from a Hamamatsu R11265 MaPMT, the baseline photon detector for the LHCb RICH upgrade, was demonstrated both with test bench measurements and with actual signals from a R11265 MaPMT. The presented results allowed CLARO to be chosen as the front-end readout chip in the upgraded LHCb RICH detector.

A CMOS Triple Inter-Locked Latch for SEU Insensitivity Design

In this paper, a novel triple inter-locked latch (TILL) design is presented, characterized with having all the single nodes insensitive to single event upset (SEU) through a robust self fault-repaired loop mechanism. A so-called SEU radiation hardening efficiency factor (SRHEF) is proposed and defined to facilitate evaluation of the overall performance for a hardened latch based not only on the SEU sensitivity but also on the area, power and delay constraints. Through such analysis, the TILL demonstrates the superior hardening efficiency in contrast to other conventional hardened latch designs. The TILL is realized and fabricated on a commercial 0.13 micron CMOS technology. According to the experiment results, the TILL is measured to have an SEU linear energy transfer (LET) threshold of above $42~\hbox{MeV} {\hbox {-}}\hbox{cm}^{2}/\hbox{mg}$ . Compared to some other hardened CMOS latches previously reported, the TILL achieves a minimum of one order of magnitude lower in terms of the SEU cross section, while on average it attains 24% speed improvement, 22% reduction in power delay product (PDP) and merely 17% more in area overhead.

DVCC Based K.H.N. Biquadratic Analog Filter with Digitally Controlled Variations

In this paper, a digitally controlled single input multi output current-mode K.H.N. Biquad Filter is presented. The filter circuit is composed of three DVCCs together with four grounded resistors and two grounded capacitors. The digital control is incorporated using a current-summing network (CSN). Tuning of resonant frequency is carried out by 3–bit digital control word. Block by block replacement has been done to observe the change in the relationship between resonant frequency of the band-pass filter with the control word. The filter circuit showed three different variations when the DVCC blocks were replaced (one by one) with 3-bit DC-DVCC blocks. PSPICE simulations using TSMC 0.25 micron CMOS technology have been performed to validate the theoretical results.

A Versatile Digitally Programmable Voltage Mode Multifunctional Biquadratic Filter

In this paper, a digitally controlled single input multi-output voltage mode multifunctional biquadratic filter is presented. The circuit makes use of only a single DVCC, two grounded capacitors, one grounded and two floating resistors. The digital control is incorporated using a current-summing network (CSN). Tuning of cut-off frequency is carried out with the help of a 3–bit digital control word. PSPICE simulations using TSMC 0.25 micron CMOS technology have been performed to validate the theoretically predicted results. General Terms Analog Signal Processing, Active Filters

Radiation hardness tests and characterization of the CLARO-CMOS, a low power and fast single-photon counting ASIC in 0.35 micron CMOS technology

The CLARO-CMOS is a prototype ASIC that allows fast photon counting with 5ns peaking time, a recovery time to baseline smaller than 25ns, and a power consumption of less than 1mW per channel. This chip is capable of single-photon counting with multi-anode photomultipliers and finds applications also in the read-out of silicon photomultipliers and microchannel plates. The prototype is realized in AMS 0.35 micron CMOS technology. In the LHCb RICH environment, assuming 10years of operation at the nominal luminosity expected after the upgrade in Long Shutdown 2 (LS2), the ASIC must withstand a total fluence of about 6×10121MeVneq/cm2 and a total ionizing dose of 400krad. A systematic evaluation of the radiation effects on the CLARO-CMOS performance is therefore crucial to ensure long term stability of the electronics front-end. The results of multi-step irradiation tests with neutrons and X-rays up to the fluence of 1014cm−2 and a dose of 4Mrad, respectively, are presented, including measurement of single event effects during irradiation and chip performance evaluation before and after each irradiation step.

Power Loss Analysis Based on Leakage Currentin PN Junctions

This paper is proposed to analyze the power loss from leakage current in p-n junctions in case of non-uniform defects. The different geometry p-n junctions have been fabricated by a standard 0.8 micron CMOS technology. The diode fabricated by the ion implantation process with two different condition. The reverse current and voltage (I-V)characteristics at varied temperature of p-n junctions have been measured. The power loss coefficient can be extracted from the leakage current versus temperature. Form the derivative of leakage current with temperature, the power loss with prediction trend curve can be obtained.

Design and Implementation of Double Base Integer Encoder of Term Metrical to Direct Binary

The digital processing signal is one of the subdivisions of the analog digital converter interface; data transfer rate in modern telecommunications is a critical parameter. The greatest feature of parallel conversion rate (4-bit parallel Flash 5/s converter) is designed and modeled in 0.18 micron CMOS technology. Low speed swing operation as analog and digital circuits leads to high speed of low power operation power with 70 mVt 1.8 V A/D converter from the power dissipated during operation in the 5 GHz range. Average offset is used to minimize the effect of the bias of a comparator. This paper contains the 8-bit encoder of the metrical term code to direct binary code decreasing power consumption, which is shown by results and comparison with other designs using computer simulation. The results of the flash ADC time-interleaved are a more significant improvement in terms of power and areas than those previously reported.

Design of Low Power Sigma Delta ADC

A Low power discrete time sigma delta ADC consisting of a second order sigma delta modulator and third order Cascaded Integrated Comb (CIC) filter is proposed. The second order modulator is designed to work at a signal band of 20K Hz at an oversampling ratio of 64 with a sampling frequency of 2.56 MHz. It achieves a signal to noise ratio of 85.2dB and a resolution of 14 bits. The CIC digital filter is designed to implement a decimation factor of 64, operating at a maximum sampling frequency of 2.56 MHz. A second order sigma delta modulator is implemented in 0.18micron CMOS technology using full custom design and the third order digital CIC decimation filter is implemented in verilog HDL. The complete Sigma Delta ADC, consisting of analog block of second order modulator and digital block of decimator consumes a total power 1.96mW.

Analysis of Gate Leakage Current in IP3 SRAM Bit-Cell under Temperature Variations in DSM Technology

In this paper, we present the temperature based simulation and analysis of gate leakage current for the proposed low-stress IP3 SRAM bit cell. In CMOS technologies, cache memory occupies a large die area and this may experience different temperatures. Under temperature variations, performance of the system may degrade. Therefore, in the IP3 SRAM cell, gate leakage has been analyzed under temperature variations. It is observed that with rise in temperature, leakage and standby power dissipation increases. The observation of the effect of temperature variations on standby power indicates that increase in standby power is minimum for P3 cell and IP3 cell, with respect to 6T and PP SRAM cells. The gate leakage observed is minimum in IP3 cell with temperature variations. This work is being carried out at deep-sub micron CMOS technology, 45nm, with tox=2.4nm, Vthn=0.22V, Vthp=0.224V, VDD=0.7V and temperature is varied from -25 0 C to +125 0 C.

Design, Modeling and Simulation of CMOS-MEMS Piezoresistive Cantilever Based Carbon Dioxide Gas Sensor for Capnometry

This paper reports design, modeling and simulation of MEMS based sensor working in dynamic mode with fully differential piezoresistive sensing for monitoring the concentration of exhaled carbon dioxide (CO2) gas in human breath called capnometer. CO2 being a very important biomarker, it is desirable to extend the scope of its monitoring beyond clinical use to home and ambulatory services. Currently the scope of capnometers and its adaption is limited by high cost, large size and high power consumption of conventional capnometers . In recent years, MEMS based micro resonant sensors have received considerable attention due to their potential as a platform for the development of many novel physical, chemical, and biological sensors with small size, low cost and low power requirements. The sensor is designed using 0.35 micron CMOS technology. CoventorWare and MATLAB have been used as simulation software. According to the developed model and simulation results the resonator has resonant frequency 57393 Hz and mass sensitivity of 3.2 Hz/ng. The results show that the longitudinal relative change of resistance is 0.24%/µm while the transverse relative change of resistance is -0.03%/µm.

A Novel Approach to Reduce the Gate and Subthreshold Leakage in a Conventional SRAM BitCell Structure at DeepSub Micron CMOS Technology

In the age of scaled silicon technology to improve the functional efficiency of a CMOS design, the device geometry and device parameters are constantly scaled. The major factors of the power consumption due to continuous reduction of the oxide thickness (tOX) is the gate leakage current in both the active and standby mode of the device and other is due to scaled supply voltage, the sub-threshold leakage current. This work proposes a novel approach called as the P3 SRAM Bit-Cell Scheme for the reduction of the active and standby leakage power through the gate and sub-threshold leakage reduction in the active and standby mode of the memory operation. As the gated transistor is of minimum feature size, so the area penalty is minimum in terms of a large memory and can be compromised. To the best of my knowledge, pMOS Gated-Ground and full-supply voltage body bias for pMOS transistor along with the PP SRAM bit-cell structure is used for the first time in the memory bit -cell design to reduce the power in 45nm CMOS technology at VDD = 0.7V and 0.8V. In comparison with the Conventional and PP SRAM Bit-cells, the active power is achieved for Write Data „0‟ as 89.21% , 94.38%, and for Write Data „1‟ as 89.23%, 94.45%, respectively at VDD = 0.7V. When the VDD = 0.8V, the active power is achieved for Write Data „0‟ as 9.15%, 93.63%, and for Write Data „1‟ as 91.68%, 93.59%, respectively.

Design of a high frequency low voltage CMOS operational amplifier

A method is presented in this paper for the design of a high frequency CMOS operational amplifier (OpAmp) which operates at 3V power supply using tsmc 0.18 micron CMOS technology. The OPAMP designed is a two-stage CMOS OPAMP followed by an output buffer. This Operational Transconductance Amplifier (OTA) employs a Miller capacitor and is compensated with a current buffer compensation technique. The unique behaviour of the MOS transistors in saturation region not only allows a designer to work at a low voltage, but also at a high frequency. Designing of two-stage op-amps is a multi-dimensional-optimization problem where optimization of one or more parameters may easily result into degradation of others. The OPAMP is designed to exhibit a unity gain frequency of 2.02GHz and exhibits a gain of 49.02dB with a 60.5 0 phase margin. As compared to the conventional approach, the proposed compensation method results in a higher unity gain frequency under the same load condition. Design has been carried out in Tanner tools. Simulation results are verified using S-edit and W-edit.

Energy-Efficient, Noise-Tolerant CMOS Domino VLSI Circuits in VDSM Technology

Compared to static CMOS logic, dynamic logic offers good performance. Wide fan-in dynamic logic such as domino is often used in performance critical paths, to achieve high speeds where static CMOS fails to meet performance objectives. However, domino gates typically consume higher dynamic switching and leakage power and display weaker noise immunity as compared to static CMOS gates. Keeping in view of the above stated problems in previous existing designs, novel energy- efficient domino circuit techniques are proposed. The proposed circuit techniques reduced the dynamic switching power consumption; short-circuit current overhead, idle mode leakage power consumption and enhanced evaluation speed and noise immunity in domino logic circuits. Also regarding performance, these techniques minimize the power-delay product (PDP) as compared to the standard full-swing circuits in deep sub micron CMOS technology. Also the noise immunity of the CMOS Domino circuits with various techniques and keepers are analyzed. Various noise sources are considered and noise immune domino logic is proposed.

LDMOSFET with drain potential suppression for 100 V Power IC technology

A standard 0.35 micrometer CMOS technology has been extended for 100 V Power IC applications by accommodating reduced surface field (RESURF) LDMOSFET device with p-well block region or extended poly-overlap region for suppression of the drain wrapping potential. A 100 V integrated H-bridge circuit suitable for driving a brushless DC motor has been designed, manufactured and tested to prove the technology. To streamline the design and integration of this power device 2D and 3D simulations have been performed. Different electrical isolation schemes to provide technology compartmentalization have also been investigated experimentally and results are discussed.

Hydrogenated Amorphous Silicon Sensor Deposited on Integrated Circuit for Radiation Detection

Radiation detectors based on the deposition of a 10 to 30 mum thick hydrogenated amorphous silicon (a-Si:H) sensor directly on top of integrated circuits have been developed. The performance of this detector technology has been assessed for the first time in the context of particle detectors. Three different circuits were designed in a quarter micron CMOS technology for these studies. The so-called TFA (Thin-Film on ASIC) detectors obtained after deposition of a-Si:H sensors on the developed circuits are presented. High internal electric fields (104 to 105 V/cm) can be built in the a-Si:H sensor and overcome the low mobility of electrons and holes in this amorphous material. However, the deposited sensor's leakage current at such fields turns out to be an important parameter which limits the performance of a TFA detector. Its detailed study is presented as well as the detector's pixel segmentation. Signal induction by generated free carrier motion in the a-Si:H sensor has been characterized using a 660 nm pulsed laser. Results obtained with a TFA detector based on an ASIC integrating 5 ns peaking time pre-amplifiers are presented. Direct detection of 10 to 50 keV electrons and 5.9 keV X-rays with the detectors are then shown to understand the potential and the limitations of this technology for radiation detection.

C-testable bit parallel multipliers over GF (2 m )

We present a C-testable design of polynomial basis (PB) bit-parallel (BP) multipliers over GF(2 m ) for 100% coverage of stuck-at faults. Our design method also includes the method for test vector generation, which is simple and efficient. C-testability is achieved with three control inputs and approximately 6% additional hardware. Only 8 constant vectors are required irrespective of the sizes of the fields and primitive polynomial. We also present a Built-In Self-Test (BIST) architecture for generating the test vectors efficiently, which eliminates the need for the extra control inputs. Since these circuits have critical applications as parts of cryptography (e.g., Elliptic Curve Crypto (ECC) systems) hardware, the BIST architecture may provide with added level of security, as the tests would be done internally and without the requirement of probing by external testing equipment. Finally we present experimental results comprising the area, delay and power of the testable multipliers of various sizes with the help of the Synopsys® tools using UMC 0.18 micron CMOS technology library.