Analysis of Gate Leakage Current in IP3 SRAM Bit-Cell under Temperature Variations in DSM Technology

Abstract

In this paper, we present the temperature based simulation and analysis of gate leakage current for the proposed low-stress IP3 SRAM bit cell. In CMOS technologies, cache memory occupies a large die area and this may experience different temperatures. Under temperature variations, performance of the system may degrade. Therefore, in the IP3 SRAM cell, gate leakage has been analyzed under temperature variations. It is observed that with rise in temperature, leakage and standby power dissipation increases. The observation of the effect of temperature variations on standby power indicates that increase in standby power is minimum for P3 cell and IP3 cell, with respect to 6T and PP SRAM cells. The gate leakage observed is minimum in IP3 cell with temperature variations. This work is being carried out at deep-sub micron CMOS technology, 45nm, with tox=2.4nm, Vthn=0.22V, Vthp=0.224V, VDD=0.7V and temperature is varied from -25 0 C to +125 0 C.