A Proposed Low Standby Power Read Disturb-Free 9T SRAM Cell

Abstract

6T SRAM Cell stability poses a major design challenge at lower technology nodes related to the standby power and also the stability. As the technology shrinks the standby power consumption increases. Also as the read current flows through the internal storage nodes, there is more chance of flipping the data at the internal storage nodes which affects the stability of SRAM cell severely. So a new 9T SRAM cell is designed with reduced standby power and decoupled read path from the internal storage nodes that eliminates the above problem. The Circuits are designed and simulated in 45nm CMOS technology using Cadence Virtuoso at 0.9V supply voltage. There is a reduction of 10.235%, 8.8511%, 7.2976%, 6.5871% standby power for the Proposed Read Disturb Free 9T SRAM(P9T) cell compared to the Conventional 6T SRAM Cell across the process corners TT, SS, FS and SF respectively. Also the stability analysis is done using the Butterfly curve across all process corners. There is a increase of 103.37%, 104.39%, 100.54%, 136.81%, 79.95% Read Static Noise margin in P9T SRAM Cell than the 6T SRAM cell at TT, FF, SS, FS and SF respectively.