Abstract
The digital processing signal is one of the subdivisions of the analog digital converter interface; data transfer rate in modern telecommunications is a critical parameter. The greatest feature of parallel conversion rate (4-bit parallel Flash 5/s converter) is designed and modeled in 0.18 micron CMOS technology. Low speed swing operation as analog and digital circuits leads to high speed of low power operation power with 70 mVt 1.8 V A/D converter from the power dissipated during operation in the 5 GHz range. Average offset is used to minimize the effect of the bias of a comparator. This paper contains the 8-bit encoder of the metrical term code to direct binary code decreasing power consumption, which is shown by results and comparison with other designs using computer simulation. The results of the flash ADC time-interleaved are a more significant improvement in terms of power and areas than those previously reported.
Highlights
Digital communication tools with high data rate, high speed broadband, radar and optical communications, these applications require 4 to 6 bit resolution at rates of 1 GHz or beyond.Several papers have been published previously in the 4-bit Flash ADC [1]
Encoder (Figure 2) consists of two CMOS—keys on the basis of transistors T1, T2 and T5, T6, which are controlled by the voltage at the input X1; Y0 determines the MSB output binary code
Power characteristics of the encoder performed using MOSFETs Cadence Virtuoso based on 180 nm CMOS technology from UMC to 1.8 V single supply [9]
Summary
Digital communication tools with high data rate, high speed broadband, radar and optical communications, these applications require 4 to 6 bit resolution at rates of 1 GHz or beyond. The multi-GHz A/D sampling rate is achieved by using interleaved time architecture. Because of the gain and offset of the inconsistencies among the various channels of ADC time-interleaved architecture usually requires numerical methods [2]. These calibrations scheme to significantly increase the power and/or Flash ADC area. The proposed architecture 5/s speed is achieved based on low swing in full operation of the ADC. No digital calibration is required, encoding to significant savings in power and scope. 21 multi-stage comparators, including 15 major and over-3 range comparators on each end of the array, compare the input signal voltage from the crane and generate code thermometer. The sample is distributed in the first latch comparator array
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