Abstract
A method is presented in this paper for the design of a high frequency CMOS operational amplifier (OpAmp) which operates at 3V power supply using tsmc 0.18 micron CMOS technology. The OPAMP designed is a two-stage CMOS OPAMP followed by an output buffer. This Operational Transconductance Amplifier (OTA) employs a Miller capacitor and is compensated with a current buffer compensation technique. The unique behaviour of the MOS transistors in saturation region not only allows a designer to work at a low voltage, but also at a high frequency. Designing of two-stage op-amps is a multi-dimensional-optimization problem where optimization of one or more parameters may easily result into degradation of others. The OPAMP is designed to exhibit a unity gain frequency of 2.02GHz and exhibits a gain of 49.02dB with a 60.5 0 phase margin. As compared to the conventional approach, the proposed compensation method results in a higher unity gain frequency under the same load condition. Design has been carried out in Tanner tools. Simulation results are verified using S-edit and W-edit.
Highlights
Over the last few years, the electronics industry has exploded
The dc gain is found to be 49.02dB and phase margin 60.50 which is good enough for an OPAMP operating at a high frequency
A unity gain frequency of 2.02GHz is excellent for an OPAMP when all the other parameters are set at an optimised value
Summary
Over the last few years, the electronics industry has exploded. The largest segment of total worldwide sales is dominated by the MOS market. Due to relatively simple circuit configurations and flexibility of design, CMOS technology has an edge over NMOS technology and is gaining rapid acceptance as the future technology for linear analog integrated circuits, especially in the telecommunication field. OPAMP can be said to be the main bottleneck in an analog circuit. They perform the function of a voltage controlled current source, with an infinite voltage gain. The design of OPAMPs continues to pose a challenge as the supply voltage and transistor channel lengths scale down with each generation of CMOS technologies [4]. Designing high-performance analog integrated circuits is becoming increasingly exigent with the relentless trend toward reduced supply voltages. Among speed, power, and gain, amid other performance parameters Often these parameters present contradictory choices for the op-amp architecture. The generic block diagram of the circuit is shown in the figure 1
Sign-in/Register to view highlights & summary Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: International Journal of VLSI Design & Communication Systems
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
