Optimization and Simulation of humidity sensor readout circuitry using two stage op amp

Abstract

In this paper a humidity sensor readout circuitry using two stage opamp is designed. This circuitry is realized in TSMC 0.18μm CMOS Technology. Designing of two-stage op-amps is a multi-dimensional- optimization problem where optimization of one or more parameters may easily result into degradation of others. The OPAMP circuit is designed to exhibit a unity gain frequency of 2.02GHz and exhibits a gain of 49.02dB with a 60.50 phase margin and CMRR 39dB, Slew Rate 154dB, UGB (Unity Gain Bandwidth) are in a higher unity gain frequency under the same load condition. Also presented humidity sensor can achieve good linearity over the relative humidity range from 20% to 80%. The total power dissipation of readout circuitry is 21.8 pW. Terms: CMOS humidity sensor, humidity sensor, Op-Amp. I. Introduction Humidity sensors have a widely used in application areas, including agriculture, climate control, food storage, and domestic appliances. In order to satisfy the requirements of these applications, humidity sensors should provide high sensitivity over a wide range of humidity and temperature and linear response. Other important parameters of the humidity sensors can be listed as long-term stability, response time, and power consumption. A desirable feature of the humidity sensors is their compatibility with standard IC fabrication technologies. There are various types of humidity sensors based on the sensing principle they use, such as resistive, mechanical, gravimetric, capacitive, and thermal humidity sensors. This approach provides a number of advantages. The diodes can be heated up with a low power, and they provide high sensitivity. As the diodes are heated up, no water condensation can occur on the sensing elements. In most of the electronics circuits the Operational Amplifiers is the most common building blocks. So as the transistor channel length and power supply is reduced then the design of Op amps face continuous challenge. Due to different aspect ratio (W/L), there is a tradeoff among speed, gain, power and the other parameters. The implementation of a CMOS OPAMPs that combines a considerable dc gain with higher unity gain frequency has been a most difficult problem. There has been several circuits design to evaluate this problem. The purpose of the design methodology in this paper is to design accurate equations for the design of high- gain 2 staged CMOS op-amp. Outline of paper