A CMOS Triple Inter-Locked Latch for SEU Insensitivity Design

Abstract

In this paper, a novel triple inter-locked latch (TILL) design is presented, characterized with having all the single nodes insensitive to single event upset (SEU) through a robust self fault-repaired loop mechanism. A so-called SEU radiation hardening efficiency factor (SRHEF) is proposed and defined to facilitate evaluation of the overall performance for a hardened latch based not only on the SEU sensitivity but also on the area, power and delay constraints. Through such analysis, the TILL demonstrates the superior hardening efficiency in contrast to other conventional hardened latch designs. The TILL is realized and fabricated on a commercial 0.13 micron CMOS technology. According to the experiment results, the TILL is measured to have an SEU linear energy transfer (LET) threshold of above $42~\hbox{MeV} {\hbox {-}}\hbox{cm}^{2}/\hbox{mg}$ . Compared to some other hardened CMOS latches previously reported, the TILL achieves a minimum of one order of magnitude lower in terms of the SEU cross section, while on average it attains 24% speed improvement, 22% reduction in power delay product (PDP) and merely 17% more in area overhead.