MESFET Research Articles

Complementary SOI MESFETs at the 45-nm CMOS Node

Silicon-on-insulator (SOI) metal-semiconductor field-effect transistors (MESFETs) with complementary n- and p-type channels have been fabricated using a commercial 45-nm CMOS process. The current drive and transconductance of the n-MESFET is approximately three times larger than that of the p-MESFET due to the higher electron mobility. Both devices operate in depletion mode with the threshold voltage of the n-MESFET being approximately -0.4 V, while that of the p-MESFET is ~0.3 V. The MESFETs have multiple gigahertz cutoff frequencies and can withstand drain bias in excess of 4 V making them attractive for analog- and mixed-signal applications that require higher operating voltages than the baseline CMOS. The p-MESFET has higher leakage current due to the lower Schottky barrier height to the p-type channel.

An improved analytical model of 4H-SiC MESFET incorporating bulk and interface trapping effects

An improved analytical model for the current—voltage (I–V) characteristics of the 4H-SiC metal semiconductor field effect transistor (MESFET) on a high purity semi-insulating (HPSI) substrate with trapping and thermal effects is presented. The 4H-SiC MESFET structure includes a stack of HPSI substrates and a uniformly doped channel layer. The trapping effects include both the effect of multiple deep-level traps in the substrate and surface traps between the gate to source/drain. The self-heating effects are also incorporated to obtain the accurate and realistic nature of the analytical model. The importance of the proposed model is emphasised through the inclusion of the recent and exact nature of the traps in the 4H-SiC HPSI substrate responsible for substrate compensation. The analytical model is used to exhibit DC I–V characteristics of the device with and without trapping and thermal effects. From the results, the current degradation is observed due to the surface and substrate trapping effects and the negative conductance introduced by the self-heating effect at a high drain voltage. The calculated results are compared with reported experimental and two-dimensional simulations (Silvaco®-TCAD). The proposed model also illustrates the effectiveness of the gate—source distance scaling effect compared to the gate—drain scaling effect in optimizing 4H-SiC MESFET performance. Results demonstrate that the proposed I–V model of 4H-SiC MESFET is suitable for realizing SiC based monolithic circuits (MMICs) on HPSI substrates.

Improved performance of 4H-silicon carbide metal semiconductor field effect transistors with multi-recessed source/drain drift regions

An improved structure of 4H-silicon carbide metal semiconductor field effect transistors with multi-recessed source/drain drift regions (MRD-MESFET) is proposed in this paper. The multi-recessed source/drain drift regions have been introduced to improve both the breakdown voltage and capacitances characteristics. Simulated results indicate that the breakdown voltage of the MRD-MESFET is 141V compared to 119V of the reported structure with only single-recessed source/drain region (SRD-MESFET). The output maximum power density is almost 19.1% larger than that of the SRD-MESFET. Also, the cut-off frequency and the maximum oscillation frequency of the proposed structure improve and are 17GHz and 68GHz compared to 15GHz and 59GHz of the SRD-MESFET due to the decrease in gate–source capacitance, respectively. The lowest gate–source capacitance and the gate–drain capacitance of the MRD-MESFET are obtained with an optimized drain deeper recessed drift region length of 0.2μm which contribute to superior RF characteristics of MESFETs.

Diamond Metal–Semiconductor Field-Effect Transistor With Breakdown Voltage Over 1.5 kV

A diamond metal-semiconductor field-effect transistor (MESFET) with a Pt Schottky gate was fabricated. The MESFET exhibited clear saturation and pinchoff characteristics. The drain current of the MESFET operated at 300 °C was 20 times higher than that at room temperature due to the activation of acceptors. The breakdown voltage was highly dependent on the gate-drain length and reached 1.5 kV at a gate-drain length of 30 μm, which is the highest reported for a diamond FET.

Dependence of the Breakdown Voltage of 4H-SiC MESFET’s on the Field Plate and Step-Channel

The breakdown mechanism of the 4H-SiC metal-semiconductor field effect transistor (4H-SiC MESFET) at a large drain bias is explored and the dependence of breakdown voltage on the field-plate and the step-channel is investigated by simulation. The results revealed that the breakdown occurs at the corner of the gate near to the drain. The channel step and the field-plate length have sensitive effect on the breakdown voltage. The breakdown characteristics are improved since the electric field peak is lowered at breakdown point in the step-channel and field-plate structures. The largest breakdown voltage can be achieved by optimizing the field-plate length.

An amazing semiconductor choice for high‐frequency FET: H‐terminated polycrystalline diamond film prepared by DC arc jet CVD

AbstractWith the development of information and communication technology, conventional semiconductors such as Si and GaAs cannot satisfy the requirement of high‐frequency and high‐power electronic devices. By contrast, diamond film has been considered to be a potential material alternative due to the highest Johnson and Keyse figures of merit. In this paper, H‐terminated polycrystalline diamond films with different quality were prepared by DC arc jet CVD through adjusting the deposition conditions. The conductive behaviour of p‐type channel on H‐terminated diamond surface was compared and analyzed based on the N‐related impurity and spontaneous polarization model. After that, MESFETs (metal‐semi‐conductor field effect transistor) were fabricated on H‐terminated diamond and the radio frequency (RF) performance was evaluated. The cut off frequency (fT) of 11 GHz and the maximum oscillation frequency (fmax) of 18.5 GHz for MESFET in our situation were obtained. It was found that equivalent circuit elements were lower or comparable with the reported values for the FETs with the highest fT and fmax except the gate capacitance, which indicates that the carrier mobility should be improved further for high‐frequency devices application. (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Au-gated SrTiO3 field-effect transistors with large electron concentration and current modulation

We report the fabrication of low-leakage rectifying Pt and Au Schottky diodes and Au-gated metal-semiconductor field effect transistors (MESFETs) on n-type SrTiO3 thin films grown by hybrid molecular beam epitaxy. In agreement with previous studies, we find that compared to Pt, Au provides a higher Schottky barrier height with SrTiO3. As a result of the large dielectric constant of SrTiO3 and the large Schottky barrier height of Au, the Au-gated MESFETs are able to modulate ∼1.6 × 1014 cm−2 electron density, the highest modulation yet achieved using metal gates in any material system. These MESFETs modulate current densities up to ∼68 mA/mm, ∼20× times larger than the best demonstrated SrTiO3 MESFETs. We also discuss the roles of the interfacial layer, and the field-dependent dielectric constant of SrTiO3 in increasing the pinch off voltage of the MESFET.

Monolithically Integrated MESFET Devices on a High-Speed Silicon Photonics Platform

We present the design and fabrication of complimentary metal-semiconductor field-effect transistors (MESFETs) monolithically integrated on a high-speed silicon photonics platform. The transistors were built in an existing silicon photonics process without any additional process steps or modifications to maintain consistent photonics performance. The MESFETs showed a threshold voltage of -1.4 and 2.0 V for NMES and PMES, respectively. The NMES transconductance was measured to be 46.4 μS/μm, and the cutoff frequency was shown to be 2.2 GHz. Transistors of this design can be simply integrated into silicon photonics platforms for on-chip feedback circuits.

Self-aligned metallization on organic semiconductor through 3D dual-layer thermal nanoimprint

High-resolution patterning of metal structures on organic semiconductors is important to the realization of high-performance organic transistors for organic integrated circuit applications. The traditional shadow mask technique has a limited resolution, precluding sub-micron metal structures on organic semiconductors. Thus organic transistors cannot benefit from scaling into the deep sub-micron region to improve their dc and ac performances. In this work, we report an efficient multiple-level metallization on poly (3-hexylthiophene) (P3HT) with a deep sub-micron lateral gap. By using a 3D nanoimprint mold in a dual-layer thermal nanoimprint process, we achieved self-aligned two-level metallization on P3HT. The 3D dual-layer thermal nanoimprint enables the first metal patterns to have suspending side-wings that can clearly define a distance from the second metal patterns. Isotropic and anisotropic side-wing structures can be fabricated through two different schemes. The process based on isotropic side-wings achieves a lateral-gap in the order of 100 nm (scheme 1). A gap of 60 nm can be achieved from the process with anisotropic side-wings (scheme 2). Because of the capability of nanoscale metal patterning on organic semiconductors with high overlay accuracy, this self-aligned metallization technique can be utilized to fabricate high-performance organic metal semiconductor field-effect transistor.

Simulation analysis of a novel dual-trench structure for a high power silicon-on-insulator metal–semiconductor field effect transistor

In this paper, a silicon-on-insulator (SOI) metal–semiconductor field-effect transistor (MESFET) by a novel dual-trench technique is presented. In the proposed technique, the dual-trench is created in the buried oxide and filled with p-type and n-type doped Si. The p-type trench beneath the source increases breakdown voltage (VBR). Also, the n-type trench beneath the gate improves the drain current (ID). We call this new structure as Dual-Trench SOI MESFET (DT-MESFET). DC and radio frequency (RF) characteristics of the proposed structure are analyzed by 2-D numerical simulation and compared with conventional SOI MESFET (C-MESFET) characteristics. The extracted results show that the dual-trench technique has excellent effect on ID, VBR, and maximum output power density (Pmax) of the device. The parameters, VBR, ID, and Pmax of the DT-MESFET structure are improved by 55.55%, 50%, and 300% compared with those of the C-MESFET structure, respectively. Also, the dual-trench technique leads to the enhancement of maximum oscillation frequency and maximum available gain. Therefore, the novel SOI MESFET structure has superior electrical characteristics as compared to the similar device based on the conventional structure.

A Microwave Modeling Oxymoron?: Low-Frequency Measurements for Microwave Device Modeling

For a number of decades, the modeling of microwave transistors relied on specific well-known characterization methods. Those methods include S-parameters measurement through vector network analyzers (VNAs) ranging from the lower end of the RF spectrum to the millimeter-wave (mm-wave) region and load pull measurements of transistors used for the design of power amplifiers (PAs). Later, the availability of more powerful computer-aided design (CAD) software enabled the need for models of active microwave devices, thus driving a huge amount of research activity on microwave transistor modeling. Simultaneously, new transistor technologies were invented, combining working concepts such as heterojunction bipolar transistors (HBTs), metal semiconductor field effect transistors (MESFETs) or high electron mobility transistors (HEMTs) and new materials such as gallium arsenide (GaAs), gallium nitride (GaN), indium phosphide (InP), and silicon germanium (SiGe), to cite only the main ones.

In–Ga–Zn–O MESFET with transparent amorphous Ru–Si–O Schottky barrier

AbstractRectifying transparent amorphous Ru–Si–O Schottky contacts to In–Ga–Zn–O have been fabricated by means of reactive sputtering without any annealing processes nor semiconductor surface treatments. The ideality factor, effective Schottky barrier height and rectification ratio are equal to 1.6, 0.9 eV and 105 A/A, respectively. Ru–Si–O/In–Ga–Zn–O Schottky barriers were employed as gate electrodes for In–Ga–Zn–O metal–semiconductor field‐effect transistors (MESFETs). MESFET devices exhibiting on‐to‐off current ratio at the level of 103 A/A in a voltage range of 2 V, with subthreshold swing equal to 420 mV/dec were demonstrated. A channel mobility of 7.36 cm2/V s was achieved. (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Modulation of over 1014 cm−2 electrons in SrTiO3/GdTiO3 heterostructures

We demonstrate charge modulation of over 1014 cm−2 electrons in a two-dimensional electron gas formed in SrTiO3/GdTiO3 inverted heterostructure field-effect transistors. Increased charge modulation was achieved by reducing the effect of interfacial region capacitances through thick SrTiO3 cap layers. Transport and device characteristics of the heterostructure field-effect transistors were found to match a long channel field effect transistor model. SrTiO3 impurity doped metal–semiconductor field effect transistors were also demonstrated with excellent pinch-off and current density exceeding prior reports. The work reported here provides a path towards oxide-based electronics with extreme charge modulation exceeding 1014 cm−2.

A novel SOI MESFET by reducing the electric field crowding for high voltage applications

In this paper, a novel silicon-on-insulator (SOI) metal–semiconductor field-effect transistor (MESFET) is presented by reducing the electric field crowding. The charge distribution in channel modifies by reducing the electric field crowding and results in the breakdown voltage (VBR) improves. To reduce the electric field crowding, a buried field plate (BFP) is employed in the buried oxide of the SOI MESFET and connected to source. DC and frequency response characteristics of the SOI MESFET with BFP (BFP-SOI MESFET) are analyzed via a 2-D numerical simulation and the results are compared with characteristics of a conventional SOI MESFET (C-SOI MESFET) structure. The BFP has outstanding effect on the VBR of the device. The VBR of the proposed BFP-SOI MESFET improves by 84% compared with that of the C-SOI MESFET. Although the saturation drain current of the proposed structure has decreased to a small extent, 37% increase in maximum power density is obtained. In addition, the proposed structure showed an approximately 70% decrease in the gate-drain capacitance (Cgd), which in-turn resulted in 5dB maximum available gain (MAG) improvement at 2GHz. As a result of employing the buried field plate, the BFP SOI-MESFET has an outstanding DC and frequency response performance compared with the C-SOI MESFET.

The Silicon Plates in Buried Oxide for Enhancement of the Breakdown Voltage in SOI MESFET

This paper introduces a novel SOI MESFET which enhancement breakdown voltage (VBR) by modifying electric field distribution. To achieve high enhancement of the VBR utilized three Silicon plates in buried oxide of the silicon on insulator metal semiconductor field effect transistor (SOI MESFET). This change in the SOI MESFET structure leads to controlled electric field distribution , increase VBR and Output Resistance (RO). The numerical simulation results show that the VBR of the Silicon Plates SOI MESFET (SP-SOI MESFET) structure improves by 50% compared with that of the conventional SOI MESFET (C-SOI MESFET) structure. As a result, the SP-SOI MESFET structure has superior electrical performances in comparison with the conventional structure.

A novel SOI MESFET by $$\uppi $$ π -shaped gate for improving the driving current

This paper introduces a novel silicon-on-insulator (SOI) metal---semiconductor field-effect transistor (MESFET) with $$\uppi $$ ? -shaped gate with triple workfunction ( $$\uppi $$ ? -SOI MESFET) to improve the DC and radio frequency characteristics. The DC and radio frequency characteristics of the proposed structure are analyzed by 2-D ATLAS international simulator and compared with a conventional SOI MESFET (C-SOI MESFET). The simulated results show that the proposed SOI MESFET has excellent effect on the breakdown voltage and the driving current. The breakdown voltage of the $$\uppi $$ ? -SOI MESFET structure gets 54 % enhancement compared with that of the C-SOI MESFET structure and also the driving current of the $$\uppi $$ ? -SOI MESFET structure gets 66.66 % enhancement compared with that of the C-SOI MESFET structure. Other main characteristics such as maximum output power density, maximum oscillation frequency and maximum available gain have been evaluated and improved in the proposed structure.

Effect of threading dislocation density and dielectric layer on temperature-dependent electrical characteristics of high-hole-mobility metal semiconductor field effect transistors fabricated from wafer-scale epitaxially grown p-type germanium on silicon substrates

We report the electrical characteristics of Schottky contacts and high-hole-mobility, enhancement-mode, p-channel metal semiconductor field effect transistors (MESFETs) fabricated on Ge epitaxially grown on Si substrates. The Ge film covers the entire underlying Si substrate at the wafer scale without mesas or limited-area growth. The device performance is characterized primarily as a function of threading dislocation density in the epitaxial Ge film (2 × 107, 5 × 107, 7 × 107, and 2 × 108 cm−2) and dielectric layers (SiO2, Al2O3, and HfO2) inserted between gate metal and Ge. The thin dielectric layers (∼1.3 nm) are used to unpin the Fermi level. The device performance improves with decreasing threading dislocation density and the use of HfO2. The hole mobility in the Ge film with 2 × 107 cm−2 dislocation density, obtained from Hall measurements, is 1020 cm2/V-s. Capacitance-voltage measurements on Schottky contacts provide the energy-dependent interfacial trap density of 6 × 1011 cm−2 eV−1, while current-voltage measurements provide an ON/OFF current ratio of 250. Based on the current-voltage characteristics of p-MESFETs, we have obtained an external transconductance of 7 mS/mm and low-field, effective hole-mobility of 307 cm2/V-s under 0.1 MV/cm at room temperature. The cut-off frequency of MESFETs is 10 GHz at 200 K and 2 GHz at 300 K. These results compare well with other reported transistor performance.

The Role of Substrate Compensation on DC Characteristics of 4H-SiC MESFET with Buffer Layer: A Combined Two-Dimensional Simulations and Analytical Study

An analytical model of 4H-SiC metal semiconductor field effect transistor (MESFET) is proposed with buffer layer on high purity semi-insulating (HPSI) 4H-SiC substrate compensated by multiple deep level traps. The contribution of deep level traps (DLT) is projected and verified using two-dimensional simulations (Silvaco®). The modeled DC characteristics are compared with two-dimensional simulations performed on the same device as considered in the analytical model.The 4H-SiC MESFET is simulated with and without the effect of buffer layer and the electron concentration profiles in different regions are observed from two-dimensional simulations.The electron concentration profiles obtained at channel-substrate interface clearly shows that when the buffer layer is not present, the channel electrons get trapped by the deep level traps used for substrate compensation. It is also observed that the inclusion of buffer layer minimizes the extent of electron trapping by screening out the active channel from the substrate. However, the trapping phenomena take place in both the cases.We believe that the proposed model of 4H-SiC MESFET which includes the substrate compensation through multiple deep level traps may be useful for realizing SiC based monolithic circuits (MMICs) on HPSI substrates.

A novel double-recessed 4H-SiC MESFET using scattering the electric field for high power and RF applications

In this paper, we present the unique features exhibited by a novel double-recessed 4H-SiC Metal–Semiconductor Field Effect Transistor (MESFET) in which the channel consists of a floating metal region (FMR-MESFET). The key idea in this work is to scatter the electric field lines and modify the ionization mechanism. The floating metal region allows more electrons participate in carrying current, so the optimized results show that the breakdown voltage (VBR) and the drain saturation current (IDsat) increase about 54% and 22% compared with a conventional double recessed MESFET (CDR-MESFET), respectively. Therefore the maximum output power density (Pmax) improved by factor 3.38 in comparisons with conventional one. Also, the cut-off frequency (fT) of 15GHz and the maximum oscillation frequency (fMax) of 135GHz for 4H-SiC FMR-MESFET is obtained compared to 13GHz and 120GHz for that of the CDR-MESFET and the minimum figure noise (Fmin) decreased as a result of reducing gate–drain and gate–source capacitances by about 42% and 40%, respectively. Therefore, the FMR-MESFET has superior RF frequency and high electrical performances.

Modeling of MESFET in SPICE including self-heating

The paper deals with the problem of modeling and analysis in Simulation Program with Integrated Circuit Emphasis of thermal effects influence on properties of metal–semiconductor field-effect transistor made of different semiconductor materials, that is, gallium arsenide and silicon carbide. An electrothermal model of the investigated transistors was formulated and experimentally verified. The proper procedure of parameter estimation for the elaborated model was carried out. The evaluation of accuracy and examination of usefulness of the elaborated model have been performed by comparison of measured and calculated devices characteristics. Copyright © 2014 John Wiley & Sons, Ltd.