MESFET Research Articles

AlGaN polarization-doped field effect transistor with compositionally graded channel from Al0.6Ga0.4N to AlN

Polarization-doped field effect transistors (PolFETs) were realized with an unintentionally doped AlxGa1-xN channel layer graded over Al compositions 0.60 ≤ x ≤ 1.0 with a maximum current density of 188 mA/mm (+10 V gate-to-source bias) and an on-resistance of 85 mΩ mm. The average mobility in the PolFET channel was estimated to be 320 cm2/V s, which exceeds that of previous AlGaN metal-semiconductor field effect transistors (MESFETs) and heterojunction field effect transistors (HFETs) of similar Al composition. The breakdown voltage was greater than 620 V, indicating an average critical electric field of >210 V/μm, which is substantially better than ∼100 V/μm that is typically achieved in GaN HFETs. These findings demonstrate that Al-rich PolFETs are attractive alternatives to MESFETs and HFETs for achieving simultaneously high channel electron density and mobility in high voltage switches.

CMOS-Compatible MESFETs for High Power RF Integrated Circuits

Metal semiconductor field effect transistors (MESFETs) have been fabricated using a 45-nm silicon-on-insulator CMOS technology available from Global Foundries. MESFETs with gate lengths of 200 nm show good manufacturability with well-controlled run-to-run variations. The DC and RF performance of devices with different drain access lengths are compared to illustrate the design trades between high breakdown voltage and high frequency operation. Two applications of the MESFETs for RF integrated circuit design are presented. The first demonstrates integrated n-channel MOSFET-MESFET cascode amplifiers that combine the enhanced voltage operation of the MESFET with the high frequency capability of the scaled MOSFET. The resulting small-signal amplifiers demonstrate cut-off frequencies of 50 GHz when operated with supply voltages of 6 V, significantly higher than the nominal 1 V breakdown voltage of the CMOS transistors. The second application demonstrates a watt-level MESFET power amplifier integrated with a CMOS current steering digital-to-analog converter (DAC). The MESFET serves as the RF output device, while the 4-bit CMOS DAC enables average power tracking. Both examples demonstrate the design flexibility enabled by the CMOS-compatible MESFETs.

Analytical modeling and simulation of a fully depleted three-gate silicon MESFET on SOI material

The three-gate (TG) silicon-on-insulator (SOI) metal–semiconductor field-effect transistor (MESFET) is proposed as an innovative type of device for use in high-density and high-speed applications. The new design is expected to exhibit excellent immunity against short-channel effects (SCEs) as well as reduced leakage current. To investigate the subthreshold characteristics of the device, a physically based analytical model for the channel potential and threshold voltage is developed based on an analytical solution of the three-dimensional Poisson equation with suitable boundary conditions. Using the model, design features including important device parameters and bias condition are examined and compared with a classical SOI-MESFET. The accuracy of the model is validated by comparison of the analytical results with the results of Silvaco simulations as well as experimental data.

Temperature Dependent Analytical DC Model for Wide Bandgap MESFETs

In this paper, an analytical model has been developed to predict DC characteristics of wide bandgap metal semiconductor field effect transistors (MESFETs). The model evaluates potential distribution inside the channel of the device by dividing the Schottky barrier depletion layer into four distinct regions and predicts I - V characteristics both at the room as well as at elevated temperatures. It also considers selfheating effects caused by the high-drain current and predicts negative output conductance, usually exhibited by wide bandgap MESFETs. The validity of the proposed technique is ensured by applying it on GaN and SiC MESFETs. It has been shown that the developed technique offers ~50% and ~37% improved accuracy in predicting the output characteristics of the device at T = 300 K and T = 500 K, respectively, relative to the best reported model. Thus, the proposed technique can be employed in the device modeling software involving high-power MESFETs.

Electrical Properties of Thermally Annealed β-Ga2O3 Metal-Semiconductor Field-Effect Transistors with Pt/Au Schottky Contacts

The electrical properties of the metal-semiconductor field-effect transistors (MESFETs) based on quasi-two-dimensional β-Ga2O3 n-channel and Pt/Au Schottky gate electrode were analyzed with cumulative temperature and time of thermal annealing. Mechanical exfoliation was used to prepare the β-Ga2O3 microflakes and the fabricated device was thermally annealed using either a rapid thermal annealing (RTA) equipment or a furnace. Raman spectroscopy was also employed to investigate the robustness of the mechanically exfoliated β-Ga2O3 microflakes. The devices survived a high temperature up to 700°C (RTA) and endured thermal annealing for an extended time of 90 minutes at 500°C. The stable performance was observed from the β-Ga2O3 MESFET until the Schottky barrier height decreased substantially and the current modulation deteriorated significantly after an RTA at 700°C. The obvious change in Schottky diode characteristics and the color contrast over the whole source and drain electrodes also confirmed the failure of MESFET operation after 120 minutes of annealing at 500°C. The thermal stability of the electronic devices based on β-Ga2O3 microflakes motivates further studies including power switching electronics under harsh environments.

Simulation and comparative analysis of the DC characteristics of submicron GaN HEMTs for use in CAD software

Bearing in mind the requirements of design engineers, a nonlinear model is developed to simulate the temperature-dependent I–V characteristics of submicron high-electron-mobility transistors (HEMTs). Self- and ambient heating effects are incorporated into the model expression to cater for both the negative and positive conductance of the device, after the onset of the saturation current. It is shown that the accuracy of numerical models previously developed for metal–semiconductor field-effect transistors (MESFETs) deteriorates when simulating the I–V characteristics of gallium nitride (GaN) HEMTs, primarily due to the self-heating effects. The validity of the proposed model is checked for GaN HEMTs with gate length ( $$L_\mathrm{g}$$ ) ranging from 0.12 to 0.7 $$\upmu \hbox {m}$$ in the temperature range of $$T=298$$ to $$T=773$$ K. It is demonstrated that the proposed model simulates, with a good degree of accuracy, the output characteristics of such devices exhibiting negative conductance in the saturation region of operation. It is observed that, for devices exhibiting negative conductance in the saturation region, the peak transconductance ( $$g_\mathrm{m}$$ ) occurs at a relatively higher negative gate bias while the peak value reduces with increasing ambient temperature. The root-mean-square errors reveal that the proposed model is better than other similar models reported in the literature, with an improvement varying from 17 to 50 % depending on the device characteristics.

An Improved UU-MESFET with High Power Added Efficiency.

An improved ultrahigh upper gate 4H-SiC metal semiconductor field effect transistor (IUU-MESFET) is proposed in this paper. The structure is obtained by modifying the ultrahigh upper gate height h of the ultrahigh upper gate 4H-SiC metal semiconductor field effect transistor (UU-MESFET) structure, and the h is 0.1 μm and 0.2 μm for the IUU-MESFET and UU-MESFET, respectively. Compared with the UU-MESFET, the IUU-MESFET structure has a greater threshold voltage and trans-conductance, and smaller breakdown voltage and saturation drain current, and when the ultrahigh upper gate height h is 0.1 μm, the relationship between these parameters is balanced, so as to solve the contradictory relationship that these parameters cannot be improved simultaneously. Therefore, the power added efficiency (PAE) of the IUU-MESFET structure is increased from 60.16% to 70.99% compared with the UU-MESFET, and advanced by 18%.

N-polar AlN buffer growth by metal–organic vapor phase epitaxy for transistor applications

We present the electrical characterization of N-polar AlN layers grown by metal–organic vapor phase epitaxy and the demonstration of N-polar AlN-channel metal–semiconductor field-effect transistors (MESFETs). A high concentration of silicon is unintentionally incorporated during the high-temperature growth of N-polar AlN, causing a high buffer leakage current. The silicon concentration decreases from 2 × 1018 to 9 × 1015 cm−3 with decreasing growth temperature, reducing the buffer leakage current to 5.6 nA/mm at a 100 V bias. The N-polar AlN MESFET exhibits an off-state drain current of 0.27 nA/mm and a transistor on/off ratio of 4.6 × 104 owing to the low leakage of AlN buffer layers.

MESFETs and inverters based on amorphous zinc-tin-oxide thin films prepared at room temperature

Room temperature fabrication of amorphous oxide semiconductors enables a cost-efficient production of devices on flexible and large-area substrates. Metal-semiconductor field-effect transistors using amorphous zinc-tin-oxide (ZTO) thin films with a cation composition of 1:1 Zn:Sn are presented. The n-type ZTO channel is deposited by long-throw magnetron sputtering from a ceramic target at room temperature on glass substrates. Reactively sputtered platinum is used as a gate contact material. We report on/off current ratios as high as 1.8 × 106, a threshold voltage of 0.47 V, and a sub-threshold swing of 124 mV dec−1 for as-fabricated devices. Using negative bias treatment, an improvement in device properties is observed, namely, a decrease in the off-current by two orders of magnitude and a reduction of the sub-threshold swing. An inverter based on as-deposited ZTO metal-semiconductor field-effect transistors exhibits a high peak gain magnitude of 119 and a small uncertainty level of 160 mV for a supply voltage of 3 V.

Effect of buffer iron doping on delta-doped β-Ga2O3 metal semiconductor field effect transistors

We report on the effect of iron (Fe)-doped semi-insulating buffers on the electron transport and DC-RF dispersion in Si delta (δ)-doped β-Ga2O3 metal-semiconductor field effect transistors. The effect of the distance between the 2-dimensional electron gas and the Fe-doped region was investigated, and Fe doping in the buffer was found to have a significant effect on the transport properties. It was found that buffers thicker than 600 nm can enable better transport and dispersion properties for field effect transistors, while maintaining relatively low parasitic buffer leakage. This work can provide guidance for the use of Fe-doped insulating buffers for future Ga2O3 based electronics.

Multivariate Regression Polynomial: A Versatile and Efficient Method for DC Modeling of Different Transistors (MOSFET, MESFET, HBT, HEMT and G4FET)

This work presents multivariate regression polynomial as a versatile and efficient method for DC modeling of modern transistors with very different underlying physics including MOSFET (metal-oxide-semiconductor field-effect transistor), MESFET (metal–semiconductor field-effect transistor), HBT (heterojunction bipolar transistor), HEMT (High-electron-mobility transistor) and a novel silicon-on-insulator four-gate transistors (G4FET). A set of available data from analytic solution, TCAD simulation, and experimental measurements for different operating conditions is used to empirically determine the parameters of this model and a different set of test data is used to verify its predictive accuracy. The developed model expresses the drain current as a single multivariate regression polynomial with its validity spanning across different possible operating regions as long as the chosen independent variables lie within the range of training data set. The continuity of the resulting polynomial and its first and second order derivatives make it particularly suitable for implementation in a circuit simulator. The model also provides a method for further simplification based on prior knowledge of the underlying physical mechanism and shows excellent predictive capability for different kinds of devices. This can be very useful for modeling deep-submicron emerging devices for which any closed-form analytical solution is not yet available.

Demonstration of a Depletion-Mode SrSnO3 n-Channel MESFET

The demonstration of SrSnO3 metal–semiconductor field effect transistors (MESFETs) is reported. The device layer structure consists a 28-nm-thick n-type SrSnO3 film on top of an 11-nm-thick undoped SrSnO3 film grown by hybrid molecular beam epitaxy on a (110) GdScO3 substrate. The MESFETs utilize a Pt Schottky gate electrode and diffused Sc Ohmic contacts. A Schottky barrier height of 1.55 eV was extracted for Pt on SrSnO3 using capacitance-voltage measurements. Devices with a gate length of $3~\mu \text{m}$ and source–drain spacing of 9 $\mu \text{m}$ had a drive current of 36 mA/mm at ${V} _{\textsf {GS}} = +1$ V and ${V} _{\textsf {DS}} = +3.5$ V, and a peak extrinsic (intrinsic) transconductance of 17 mS/mm (35 mS/mm).

P-GaAs Nanowire Metal–Semiconductor Field-Effect Transistors with Near-Thermal Limit Gating

Difficulties in obtaining high-performance p-type transistors and gate insulator charge-trapping effects present two major challenges for III-V complementary metal-oxide semiconductor (CMOS) electronics. We report a p-GaAs nanowire metal-semiconductor field-effect transistor (MESFET) that eliminates the need for a gate insulator by exploiting the Schottky barrier at the metal-GaAs interface. Our device beats the best-performing p-GaSb nanowire metal-oxide-semiconductor field effect transistor (MOSFET), giving a typical subthreshold swing of 62 mV/dec, within 4% of the thermal limit, on-off ratio ∼105, on-resistance ∼700 kΩ, contact resistance ∼30 kΩ, peak transconductance 1.2 μS/μm, and high-fidelity ac operation at frequencies up to 10 kHz. The device consists of a GaAs nanowire with an undoped core and heavily Be-doped shell. We carefully etch back the nanowire at the gate locations to obtain Schottky-barrier insulated gates while leaving the doped shell intact at the contacts to obtain low contact resistance. Our device opens a path to all-GaAs nanowire MESFET complementary circuits with simplified fabrication and improved performance.

A Novel SOI MESFET to Improve the Equipotential Contour Distributions by Using an Oxide Barrier

A new Metal Semiconductor Field Effect Transistor (MESFET) structure in Silicon on Insulator (SOI) technology will be introduced in this paper. In our idea, an oxide barrier is used on the drain side of the gate to improve DC and AC characteristics of MESFETs. We call the proposed structure as modified equipotential contour MESFET (MEC-MESFET). Our main reason to present this proposed structure is to modify the equipotential contour distributions by using the oxide barrier. In addition, the oxide barrier has a greater energy band gap rather than a silicon (Si) semiconductor. So, in comparison with Si, it will break at higher voltages. The maximum electric field occurs on the gate edge near the drain side in a conventional MESFET (C-MESFET). Therefore, in the proposed structure, by placing an additional oxide barrier in the drain side of the gate and modifying the maximum electrical field in this part, the breakdown voltage increases. The drain saturation and breakdown voltage of the proposed structure improve 21 and 29 percent, respectively, which increases the maximum output power density to 56 percent in comparison with conventional silicon on insulator MESFET (C-MESFET). Moreover, the gate capacitance decreases by using the oxide barrier and consequently improves the frequency characteristics like Unilateral power gain (U), Maximum Available Gain (MAG), current gain (h21), and noise in comparison with the C-MESFET.

SOI-MESFET with a layer of metal in buried oxide and a layer of SiO2 in channel to improve RF and breakdown characteristics

A novel silicon on insulator metal semiconductor field effect transistor (SOI MESFET) structure is presented in this paper. The proposed structure includes a thin layer of nickel located in the buried oxide (BOX) of the structure which causes RF parameters to experience improved values. A thin layer of oxide in the channel under the gate edge near the drain, controls the electric field distribution and has considerable effect on the breakdown voltage. The breakdown voltage is increased by 53%. In addition, the maximum output power density is improved by 148%. The gate capacitances are reduced as a result of decreasing the depletion region extension into source and drain regions and due to the effect of metallic region in the BOX. So the proposed structure has better RF and high voltage characteristics compared to the conventional structure in terms of breakdown voltage, maximum oscillation frequency, cut-off frequency, and maximum output power density.

Characterisation of a Schottky ISFET as Hg-MOSFET and as cytochrome P450-ENFET

ABSTRACTA cost-effective and simple method is proposed wherein a Schottky ion sensitive field effect transistor (Schottky ISFET)-based sensor is characterised as metal oxide semiconductor and enzyme field effect transistor (ENFET). This technique involves deposition of mercury (Hg) as gate material over the sensing layer mitigating the complexity of fabrication process, thereby eliminating the need of refabricating an identical device. A Schottky-based ISFET simplifies the fabrication process as the requisite for doping of source and drain regions becomes redundant. Steps involved in lithography process for fabricating metal oxide semiconductor field effect transistor (MOSFET) are reduced with the use of liquid metal Hg as gate over layer. Such a device can be transformed back to an ISFET without any additional etching process. Furthermore, the same ISFET device can be utilised as an ENFET when the former is used in conjunction with a biological element. In this work, a Schottky-based ISFET has been characterised as Hg-MOSFET and as cytochrome P450-ENFET. Multiple tests on the device exhibit that the same ISFET sensor can be used both as a MOSFET and an ENFET with good repeatability and versatility without losing its sensitivity.

<inline-formula> <tex-math notation="LaTeX">$K$ </tex-math> </inline-formula>-Band CMOS-Based MESFET Cascode Amplifiers

Cascode amplifiers consisting of a common-source MOSFET integrated with a common-gate metal–semiconductor field-effect transistor (MESFET) have been manufactured using a commercial 45-nm silicon-on-insulator RF CMOS process. The enhanced breakdown voltage of the MESFETs combined with the high speed of the RF MOSFETs, results in a maximum cutoff frequency of up to 70 GHz, with a maximum available gain of 18 dB at K-band frequencies (18–27 GHz) using a 6-V supply. This high-frequency operation makes the proposed amplifier a prospective candidate for 5G and millimeter wave applications.

Electric Field Characterization of Diamond Metal Semiconductor Field Effect Transistors Using Electron Beam Induced Current

Lateral gate depletion expansion towards drain contact has been analyzed on p-type diamond metal-semiconductor field effect transistor by electron beam induced current. The investigation was restricted to a closed channel to simplify the study and to directly observe the expansion of the lateral depletion region. The experimental data agreed with the theoretical model given in the literature.

Metal Semiconductor Field Effect Transistors with Conducting NbS2/n-MoS2 Van Der Waals Schottky Junction and Graphene Contact

We have fabricated van der Waals (vdW) Schottky junction between high work function conducting NbS2 transition metal dichalcogenide (TMD) and semiconducting n-MoS2 TMD for metal semiconductor field effect transistors (MESFETs). The Schottky barrier between NbS2 and MoS2 appeared as large as ~0.5 eV due to their work function difference, as measured by scanning Kelvin probe. Schottky effect MESFET operates with a low threshold gate voltage of -0.5 ~ -1 V exhibiting easy saturation. Since this FET contains low density traps at the vdW interface, little gate hysteresis and ideal subthreshold swing of 60~80 mV/dec are expected. In addition, source/drain (S/D) contact for n-channel MoS2 could significantly affect device mobility. In the case of the graphene S/D contact, the device shows the highest mobility of more than 800 cm2/V s, although the device shows the lowest mobility of ~15 cm2/V s in the case of Au/MoS2 contact without an annealing process. TMD-based MESFET with NbS2/n-MoS2 junction is considered novel and promising in future 2D device electronics.

Thermal Stability of Quasi-Two-Dimensional β-Ga2O3 and Its Device Application

An ultra-wide bandgap of around 4.8-4.9 eV (at room temperature), high thermal and chemical stabilities are some of the attractive properties of β-gallium oxide (β-Ga2O3) for fabricating (opto)electronics. Its noticeably high dielectric breakdown field (Ebr) also has drawn attention; the theoretical value was calculated to be ~8 MV/cm and a recent report reached an experimental value of 3.8 MV/cm, which is higher than those of GaN and SiC. These advantages obviously led to various applications on power devices including metal-semiconductor field-effect transistors (MESFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs) and Schottky barrier diodes. Mechanically exfoliated β-Ga2O3 flakes were studied in our investigation. The mechanical exfoliation of β-Ga2O3 is possible although it is not formed by van der Waals interaction as its monoclinic structure allows cleavage into thin flakes along [100] direction. This new possibility of preparing β-Ga2O3 samples not only suggests that β-Ga2O3 can possess two-dimensional (2D) properties, but also offer a solution for low thermal conductivity of β-Ga2O3, which is a critical limitation when fabricating high power devices. Since it is only recently that mechanically exfoliated β-Ga2O3 gained attention, there still exists several characteristics to be investigated. Unlike bulk substrates, quasi-2D β-Ga2O3 needs more research on stability to be applied to devices such as sensors and high-power electronics that operate at high temperature. In this study, the thermal stability of β-Ga2O3 flakes was observed over time and the means to improve the stability were investigated. The optical and structural changes with time were measured as the samples were exposed to higher temperature (200 – 400 °C). MESFETs were also fabricated using β-Ga2O3 flake as the channel material to investigate the thermal effects on the device, especially the Schottky barrier between the channel and the gate metal. Different metals and an additional thermally conductive 2D layer was used to enhance the thermal stability of the device. This study shows the potential of quasi-2D material (β-Ga2O3) devices with long term stability at high temperature. Further results and discussion will be presented in detail.