MESFET Research Articles

Improvement in the performance of SOI-MESFETs by T-shaped oxide part at channel region: DC and RF characteristics

In this paper, a new structure for silicon on insulator (SOI) metal semiconductor field effect transistor (MESFET) is proposed. This new structure improves DC and RF characteristics of the device by embedding a region of hafnium oxide which is shaped like a reversed T letter in the channel region. This structure is named SOI-MESFET with T-Shaped oxide part (T-SOP). Hafnium oxide region increases the breakdown voltage of the device due to its higher critical electric field in comparison with silicon used in the conventional structure (C-SOI MESFET). The breakdown voltage of the conventional structure is 14 V while it raises to 19.5 V in proposed structure. Furthermore, placing this region in the channel, increases the operating frequencies of the device due to the modification in capacitances. Studying the maximum output power density shows that the proposed structure causes 31.5% improvement compared with the C-SOI MESFET. To improve the device performance, dimensions of the oxide region have been optimized and the more optimum performance achieved by varying the dimensions and finding the most suitable values. Due to the mentioned superiorities of the proposed structure over its conventional counterpart, it can be said that the proposed structure has the capability to be used as a reliable alternative for C-SOI MESFET in high voltage and high frequency applications. Also, from fabrication point of view, a fabrication process flow for T-SOP structure is proposed which shows convenient steps to develop this device.

High temperature operation of n-AlGaN channel metal semiconductor field effect transistors on low-defect AlN templates

We report room-temperature to 200 °C operation of n-Al0.65Ga0.35N channel metal semiconductor field effect transistors (MESFET) grown over high-quality AlN/sapphire templates. For this temperature range, the source-drain currents, threshold voltages, and dc-transconductance values remain nearly unchanged with an estimated field-effect mobility of ∼90 cm2/V-s at 200 °C and currents of >100 mA/mm. The analysis of the temperature dependent current-voltage characteristics of the gate-source Schottky barrier diode reveals that the leakage currents arise from Frenkel-Poole emission. The capacitance-voltage data show no hysteresis, indicating a high quality Schottky barrier interface. These MESFET's have excellent potential for use as a high temperature power electronic or a solar-blind ultraviolet sensing device.

(Invited) Low-Temperature Processed InGaZnO MES-FET for Flexible Device Applications

An In–Ga–Zn–O metal-semiconductor field-effect transistor (IGZO MES-FET) with an AgOX Schottky gate was demonstrated at a maximum processing temperature of 150°C. We investigated the effects of the O2 gas flow ratio during the IGZO deposition and the post-IGZO-deposition annealing temperature on electrical properties of the MES-FETs. When the MES-FET was fabricated at room-temperature process, the on current of the MES-FETs strongly depended on the partial pressure of oxygen during the IGZO deposition. In contrast, the on current of the MES-FETs improved drastically by applying the post-deposition annealing at 150ºC. The post-deposition annealing is an effective method to improve the electrical properties and processing window of the IGZO MES-FET.

X-band power amplifier for next generation networks based on mesfet

Advanced wireless standards of communication like 3GPP and LTE are becoming more and more efficient and with this evolution of communication systems mobile equipment is also become smaller and smaller. Power amplifier designing has become a very crucial task in this era where efficiency and size are the main concern of any designer. In this paper we have design and analyzed X-band Class E Metal-semiconductor field effect transistor (MESFET) based Power Amplifier. This device targets the devices which use OFDM technique to improve their spectral efficiency for the next generation communication systems. Microstrip lines are used to achieve small size for our design instead of lumped components. Load Pull measurements are used to get MESFET input and output impedances optimum values. For linear and non linear operation small signal mathematical model of the design is used. To reduce thermal losses FR4 substrate is used to increase PA efficiency. Our designs shows small values of input and output return loss of about -22.3dB and -23.716 dB achieving a high gain of about 25.6 dB respectively, with PAE of about 30 % having stability factor greater than 1 and 21.894dBm of output power

Design and function of GaN MESFET terahertz signal generator by finite difference method

The GaN based metal semiconductor field effect transistor (MESFET) devices have been designed by employing finite difference method in order to fit quite well for generation of terahertz signals. The equipotential and equi-electric field contours are broadly developed with variation of drain and gate voltages. The motion of Gunn domain with variation of voltage is constantly observed from source to drain in the channel area of MESFET. In fact, the domain is more clearly visible in the equi-electric field contours than that in the equipotential contours. The distribution of electron concentration (n) in the MESFET is also determined in the steady state mode by fitting right successive relaxation factor and electron relaxation time. The I-V curves of drain are tested by employing Gummel process in finite difference method. The MESFET device is designed in such way to obtain 26.5GHz output signal in the millimeter region by tailoring its physical parameters such as geometry of device, carrier concentration, mobilities etc.

Frequency performance of a SiC MESFET with a moderately doped buffer layer

ABSTRACTIn this work, we study the impact of a moderately doped P buffer layer below N-type active channel of a Silicon Carbide Metal Semiconductor Field Effect Transistor (SiC MESFET)​​​​​ on its frequency performance. The effect of depletion layer width in the channel developed at the channel–buffer junction has been investigated assuming two separate field regions under the gate. An improved method to calculate mutual and drain conductance of the device is suggested for conventional two-region model. The cut-off frequency and maximum frequency of the device have been calculated and their variations over buffer layer doping density have been presented. The theoretically calculated values of cut-off frequency and maximum frequency of the device have been compared with the experimental value reported earlier and a considerably good agreement has been observed.

Zinc tin oxide metal semiconductor field effect transistors and their improvement under negative bias (illumination) temperature stress

Metal-semiconductor-field-effect-transistors (MESFETs) with silver oxide Schottky gates on zinc tin oxide (ZTO) channels showed fundamental differences in stability compared to conventional amorphous-oxide semiconductor thin-film-transistors (AOS-TFTs). The most severe negative-bias-temperature and negative-bias-illumination-temperature stress conditions, which usually degrade the performance of AOS-TFTs, significantly improved the switching characteristic of these ZTO MESFETs, producing devices with on:off current ratios, mobilities, and subthreshold swings of 8 × 106, 12 cm2 V−1 s−1, and 180 mV/dec, respectively. Further analysis confirmed that both negative bias and temperature (65 °C) were simultaneously required to produce this permanent effect that was linked to the electromigration of ionized donors from the MESFET depletion-region.

High Voltage GaN Lateral Photoconductive Semiconductor Switches

High voltage (>4000 V) GaN lateral photoconductive semiconductor switches (PCSSs) were developed and characterized. The epitaxial structure consisted of 1.4 μm of semi-insulating GaN grown on a SiC substrate. Intrinsic mode operation, where above bandgap light is used to trigger the PCSS, results in the highest amount of photocurrent. These PCSSs can also be triggered in extrinsic mode, where sub-bandgap illumination excites carriers from extrinsic defect levels, but this results in a significantly lower photocurrent. Triggering at near bandgap with 10 V applied, the on-state photocurrent is over eight magnitudes higher than the dark off-state leakage, indicating extremely high responsivity. A 293 nm picosecond pulse width laser was used to determine the rise time of the PCSS to be ∼160 ps. Various geometry devices were fabricated, and the low voltage on-state current obeyed a linear trend as a function of perimeter/gap optically while optically gating the PCSS, which is analogous to the width/length of a metal oxide semiconductor field effect transistor. Off-state breakdown voltages >4000 V were achieved and were likely limited by the thickness of the GaN epitaxial layer.

Successfully Controlled Potential Distribution in a Novel High-Voltage and High-Frequency SOI MESFET

Potential distribution of a silicon-on-insulator metal-semiconductor field effect transistor (SOI-MESFET) is successfully controlled by introducing a new structure. The structure we established, utilizes a P-type layer embedded in the drift region. Also, the doping engineering is applied to the proposed structure in order to more enhance the performance superiority of the novel structure called SPL-DE SOI MESFET. The P-type layer and doping engineering control the potential distribution and help the proposed structure to improve the important parameters, such as breakdown voltage, driving current, power gains, oscillation frequency, transconductance, maximum output power density, and gate-drain parasitic capacitance. As a result, the SPL-DE SOI MESFET has superior electrical performances in comparison with the similar device based on the conventional structure thus taking into account the special considerations for the high-voltage and high-frequency applications.

A novel 4H-SiC MESFET with serpentine channel for high power and high frequency applications

In this paper, a novel 4H-SiC metal semiconductor field effect transistor with serpentine channel (SC-MESFET) is proposed which the gate-drain drift region shifts downward integrally compared to the gate-source drift region. With the depth of the gate-drain shift increasing, the channel electric field and the gate depletion layer have been modulated. The simulated results show that the drain saturation current and breakdown voltage of the SC-MESFET are about 21.5% and 46.7% larger than that of the conventional double-recessed 4H-SiC MESFET (DR-MESFET). The gate-source capacitance of proposed structure is also improved from 0.59 pF/mm to 0.51 pF/mm and the DC transconductance of the SC-MESFET is very close to that of the DR-MESFET at the bias conditions of Vgs = 0 V and Vds = 40 V, which results in better RF characteristics. All of the results show that the novel 4H-SiC MESFET with serpentine channel has superior electrical characteristics and performances.

Effect of temperature on (TV) statics characteristics of GaAs Mesfet

The GaAs metal semiconductor field effect transistors called mesfets are the most active components used in microwave applications. To better exploit the performance of these components circuits, it is necessary to develop techniques for sophisticated numerical computation based on physical mechanisms that govern the operation of these devices. The static properties of GaAs MESFET could be determined from an original analytical study based on the resolution of the semiconductor fundamental equations. Then we will study the equation of thermal resistance as a function of the physical parameters of MESFETs by analogy electric thermal resistance RTH will be determined as the ratio of the difference of temperature on the thermal dissipation. The model took into account the difference between the temperature of the component and the ambient temperature and the effect of temperature on the parameters of the component.

Impact Ionization in SOI MESFETs at the 32-nm Node

Silicon metal–semiconductor FETs (MESFETs) have been fabricated using a 32-nm silicon-on-insulator (SOI) CMOS technology. The MESFET gates are formed during the self-aligned silicide step and show almost ideal Schottky behavior at low drain voltages. However, an anomalous peak in the reverse gate leakage current appears for drain voltages ≥2 V. The anomalous gate current is attributed to impact ionization generating excess holes that exit the channel through the Schottky contact. An analytical model is used to extract the electron impact ionization rate, $\alpha $ , which agrees with three earlier data sets over nearly four orders of magnitude.

On the design of GaN vertical MESFETs on commercial LED sapphire wafers

Design of GaN-based vertical metal-semiconductor field-effect transistors (MESFETs) on commercial light-emitting-diode (LED) epi-wafers has been proposed and proof of principle devices have been fabricated. In order to better understand the IV curves, these devices have been simulated using the charge transport model. It was found that shrinking the drain pillar size would significantly help in reaching cut-off at much lower gate bias even at high carrier concentration of unintentionally doped GaN and considerable leakage current caused by the Schottky barrier lowering. The realization of these vertical MESFETs on LED wafers would allow their chip-level integration. This would open a way to many intelligent lighting applications like on-chip current regulator and signal regulation/communication in display technology.

Low-Temperature Processed Metal-Semiconductor Field-Effect Transistor with In-Ga-Zn-O/AgOx Schottky Gate

Amorphous oxide semiconductors (AOSs), such as In-Ga-Zn-O (IGZO), are expected to be used as a channel material for thin-film transistors (TFTs) because the IGZO TFTs exhibit field-effect motilities (μFE) of over 10 cm2/Vs and good uniformity even fabricated at room temperature [1]. Metal-insulator-semiconductor field-effect transistor (MIS-FET) has been employed widely for the IGZO MIS-FET. However, processing temperature of 300-400 °C is required to guarantee the performance and reliability of the IGZO MIS-FET. In comparison with the MIS-FET, metal-semiconductor field-effect transistor (MES-FET) has several advantages such as low processing temperature since Schottky gate can be formed at low temperature. Thus, the IGZO MES-FET is a good candidate for flexible device applications. However, there is only a few reports for AOSs based MES-FET due to difficulty of the formation of stable and good Schottky contacts with AOSs [2, 3]. Previously, we reported the top-gate coplanar MES-FETs with an IGZO channel, which was deposited by mist chemical vapor deposition, and sputtered AgOx Schottky gate [4]. A μFE of 3.2 cm2/Vs and a subthreshold swing of 356 mV/decade were achieved. However, the maximum processing temperature of reported MES-FET was 350 °C. In this study, we fabricated MES-FET with room-temperature deposited sputtered IGZO channel. We investigated the effect of O2 gas flow ratio during the IGZO deposition and mid-annealing at 200 °C. A 100-nm-thick IGZO channel was deposited by dc magnetron sputtering in the mixture of Ar/O2 gas at room temperature, using a ceramic target (In2O3 : Ga2O3 : ZnO = 1 : 1: 1 atm.%). The O2 gas ratio was chosen at 1 and 0.8 % at a deposition pressure of 1 Pa. After patterning of the IGZO channel, one of the IGZO deposited at 1 % of O2 was annealed in air at 200 °C for 1 hour. Then, an AgOx Shcottky gate was deposited by reactive sputtering at room temperature and Au was deposited on the AgOx. Finally, source and drain electrodes were formed by Mo. Fig. 1 shows I-V characteristics of the Schottky diode. The rectification ratio (VG = ±2 V) of IGZO (1% O2) and IGZO (0.8 % O2) and IGZO (1 % O2+mid-annealing at 200 °C) was 2.3×106, 2.1×107, 3.3×107, and ideality factor was 1.75, 1.41, 1.39, respectively. Fig. 2 shows transfer characteristics of the IGZO MES-FETs with W/L of 100/10 µm. The electrical properties of the TFTs and Hall effect measurement results of IGZO channels were summarized in Table I. From the TFT characteristics, it was confirmed the Von shifted from 0.4 to 0.2 V when O2 ratio decrease from 1 to 0.8 %. When the IGZO was annealed at 200 °C, the on-current markedly increased accompanied by the negative Von shift. The μFE of the IGZO MES-FET, Hall carrier concentration and Hall mobility of the IGZO films were also summarized in Table I. The μFE and Von of the IGZO MES-FET were well correlated with the Hall mobility and carrier concentration of the IGZO channel, respectively. Detail of the results will be discussed in the conference. Acknowledgement Authors would like to thank Drs. Giang T. Dang and Martin W. Allen, University of Canterbury, New Zealand, for their helpful discussions regarding formation process and mechanism of the Schottky contact with AOS. [1] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, “Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors,” Nature, vol. 432, no. 25, pp. 488–492, (2004). [2] M. Lorenz, A. Lajn, H. Frenzel, H-V. Wenckstern, M. Grundmann, P. Barquinha, R. Martins. And E. Fortunato, “Low-temperature processed Schottky-gated field-effect transistors based on amorphous gallium-indium-zinc-oxide thin films” Appl. Phys. Lett., vol. 97, no. 10, pp. 243506-1–243506-3, (2010) [3] D-H. Lee, K. Nomura, T. Kamiya, and H. Hosono, “Metal-Semiconductor Field-Effect Transistor Made Using Amorphous In-Ga-Zn-O Channel and Bottom Pt Schottky Contact Structure at 200°C” ECS Solid State Lett., vol. 1, no. 1, pp. Q8–Q10, (2012). [4] G-T. Dang, T. Kawaharamura, M. Furuta, Member, IEEE, and M-W. Allen, “Metal–Semiconductor Field-Effect Transistors With In–Ga–Zn–O Channel Grown by Nonvacuum-Processed Mist Chemical Vapor Deposition,” IEEE Electron Device Lett., vol. 36, no. 5, pp. 463-465 (2015). Figure 1

Low-Temperature Processed Metal-Semiconductor Field-Effect Transistor with In-Ga-Zn-O/AgOx Schottky Gate

In this study, metal-semiconductor field-effect transistor (MES-FET) with an In-Ga-Zn-O/AgOX Schottky gate was fabricated at 200 °C. We investigated the effects of O2 gas flow ratio during the IGZO deposition and post-IGZO annealing in air at 200 °C on electrical properties of the MES-FET. The rectification ratio (± 2 V) of over 1.0×108 and ideality factor of 1.29 were achieved for the IGZO/AgOX Schottky diode when the post-IGZO annealing was applied at 200 °C. The IGZO MES-FET was successively fabricated at a maximum processing temperature of 200 °C with good electrical properties such as an on/off current ratio of 3.6×107, field effect mobility of 13.8 cm2/Vs, and subthreshold swing of 96 mV/decade. Moreover, the IGZO MES-FET exhibited good reliability under positive bias stress. Thus, the IGZO MES-FET is a potential candidate for flexible device application.

Novel 4H-SiC MESFET with modified depletion region by dual well for high-current applications

We describe herein a 4H-SiC metal---semiconductor field-effect transistor (MESFET) with a novel dual well in the buffer layer. The key idea is to change the channel thickness to decrease the hole concentration and modify the depletion region shape and drain current path in the channel. In the proposed structure, a dual well is created in the buffer layer exactly under the gate. We call this structure the dual-well MESFET (DW-MESFET). The drain current of the proposed structure increases by 34.7 % compared with the conventional structure (C-MESFET) due to the change in channel thickness and modification of the depletion region and drain current path. Also, the maximum power density ($$P_{\mathrm{max}}$$Pmax) and the direct-current (DC) transconductance ($$g_{\mathrm{m}}$$gm) of the DW-MESFET increase by 45.23 and 72.5 %, respectively, in comparison with the C-MESFET structure. Hence, the proposed structure can be used for high-current and high-power applications.

A novel 4H-SiC MESFET with double upper gate and recessed p-buffer

A novel structure named 4H-SiC metal semiconductor field effect transistor with double upper gate and recessed p-buffer (DURP MESFET) is proposed and simulated in this paper. The increase in the saturation drain current and the breakdown voltage, and the decrease in the gate-source capacitance are achieved compared with those of DR MESFET, which are result from the reduction of the depletion region under the gate by the introduction of a double upper gate. The negative influence of the double upper gate on trans-conductance is suppressed by employing a recessed p-buffer. With the optimal size, the height of the upper gate Z = 0.10 μm, the depth and width of the recessed p-buffer of 0.05 μm and 0.35 μm, superior DC and RF characteristics for the proposed structure can be obtained, such as a 22.5% increase in the saturation drain current and a 17.9% increase in the breakdown voltage compared to the DR MESFET. The gate-source capacitance is 0.439 pF/mm compared to 0.573 pF/mm of DR MESFET by reference to simulated results, which would lead to the DURP MESFET has excellent RF performance.

Characteristics of GaAs Power MESFETs with Double Silicon Ion Implantations for Wireless Communication Applications

GaAs power metal-semiconductor field-effect transistors (MESFETs) were fabricated using direct double silicon (Si) ion implantation technology for wireless communication applications. A 150-µm MESFET had a saturation drain current of 238 mA/mm after Si3N4passivation. A 15-mm MESFET, when measured under a class-AB condition with a biased drain voltage of 3.4 V and a quiescent drain current of 600 mA, delivered a maximum output power (Pout) of 31.1 dBm and a maximum power-added efficiency (PAE) of 58.0% at a frequency of 1.88 GHz. The MESFET exhibited aPoutof 29.2 dBm with a PAE of 45.0% at the 1-dB gain compression point. The MESFET, when measured under a deep class-B condition with a biased drain voltage of 4.7 V and a quiescent drain current of 50 mA, achieved a maximumPoutof 33.1 dBm and a maximum PAE of 55.9% at 1.88 GHz. The MESFET operating at 4.7 V and 1.88 GHz exhibited aP1dBof 31.8 dBm and an associated PAE of 47.1% at the 1-dB gain compression point. When tested by IS-95 code-division multiple access (CDMA) standard signals and biased at 4.7 V under the deep class-B condition, the MESFET with aPoutof 28 dBm demonstrated an adjacent channel power rejection (ACPR) of –31.2 dBc at +1.25 MHz apart from the 1.88 GHz center frequency and –45.7 dBc at +2.25 MHz.

Increase in the scattering of electric field lines in a new high voltage SOI MESFET

This paper illustrates a new efficient technique to enhance the critical features of a silicon-on-insulator metal-semiconductor field-effect transistor (SOI MESFET) applied in high voltage applications. The structure we proposed utilizes a new method to scatter the electric field lines along the channel region. Realization of two trenches with different materials, which a trench is created in the channel region and the other one is created in the buried oxide, helps the proposed structure to improve the breakdown voltage, driving current, drain-source conductance, minimum noise figure, unilateral power gain and output power density. Exploring the obtained results, the proposed structure has superior electrical performance in comparison to the conventional structure.

Ring Oscillators Based on ZnO Channel JFETs and MESFETs

Ring oscillator circuits based on junction field‐effect transistors as well as metal–semiconductor field‐effect transistors with ZnO channels are presented. Single stage delay times down to 110 ns are observed. The experimental oscillation frequencies are related to easily measurable device properties by a simple analytical model. This work proves the feasibility of low power oxide based circuits with Schottky diode and bipolar (pn‐) diode gates since both approaches provide significantly lower operation voltages at similar frequencies compared to previously reported oxide thin film transistors based on insulating gates.