Metal Oxide Semiconductor Structures Research Articles

Study of radiation damage induced by 12 keV X-rays in MOS structures built on high-resistivityn-type silicon

Imaging experiments at the European X-ray Free Electron Laser (XFEL) require silicon pixel sensors with extraordinary performance specifications: doses of up to 1 GGy of 12 keV photons, up to 10(5) 12 keV photons per 200 µm × 200 µm pixel arriving within less than 100 fs, and a time interval between XFEL pulses of 220 ns. To address these challenges, in particular the question of radiation damage, the properties of the SiO(2) layer and of the Si-SiO(2) interface, using MOS (metal-oxide-semiconductor) capacitors manufactured on high-resistivity n-type silicon irradiated to X-ray doses between 10 kGy and 1 GGy, have been studied. Measurements of capacitance/conductance-voltage (C/G-V) at different frequencies, as well as of thermal dielectric relaxation current (TDRC), have been performed. The data can be described by a dose-dependent oxide charge density and three dominant radiation-induced interface states with Gaussian-like energy distributions in the silicon band gap. It is found that the densities of the fixed oxide charges and of the three interface states increase up to dose values of approximately 10 MGy and then saturate or even decrease. The shapes and the frequency dependences of the C/G-V measurements can be quantitatively described by a simple model using the parameters extracted from the TDRC measurements.

Specific features of silicon surface region fluorination by RIE in r.f. CF4 plasma – A novel method for improving the electrical properties of thin PECVD silicon oxide films

► Comparison of fluorine plasma implantation methods have been performed. ► Classical PECVD and RIE reactors were used for ultra-shallow implantation. ► Observed changes were determined by ULE-SIMS and electrical ( C – V and I – V ) methods. ► PECVD SiO 2 was used as gate dielectric layer in MOS structures. ► Fluorination in RIE results in better electrical behavior of MOS structures. In this study, we compare a previously reported method of improving the electro-physical properties of silicon dioxide (SiO 2 ), which uses silicon substrate fluorination in CF 4 in a Plasma Enhanced Chemical Vapor Deposition (PECVD) reactor prior to oxide deposition, with our proposed method of fluorination in CF 4 in a classical Reactive Ion Etching (RIE) reactor. The careful analysis of the location and behavior of fluorine profile during PECVD gate oxide deposition was done by means of Ultra Low Energy-Secondary Ion Mass Spectroscopy (ULE-SIMS). The observed effects were used to determine changes in the electrical properties of the dielectric layers from the two fluorination methods being studied. The results showed that, in general, fluorination in a RIE reactor is superior to fluorination in a PECVD reactor. The advantage of the former technique is that most of the electro-physical properties of the resulting Metal–Oxide-Semiconductor (MOS) structures are significantly better. The change in the properties of gate stacks was shown to be fluorine concentration dependent, which can be controlled by the parameters of the RIE (e.g., by r.f. power supplied to the discharge). However, this study concluded that the fluorine profile parameters cannot be controlled independently.

The influence of oxygen ambient annealing conditions on the quality of Al/SiO2/n-type 4H-SiC MOS structure

The effect of reoxidation process in O2 on the electrical properties of metal-oxide-semiconductor (MOS) capacitors fabricated on n-type 4H-SiC (0 0 0 1) is investigated. All samples were oxidized in wet oxygen at temperature of 1175 °C. Reoxidation process was carried out on four of the five samples. Samples were annealed at temperature of 700 °C and 800 °C for different process times. The reoxidation process in oxygen improves the quality of the dielectric layer and the interface of Al/SiO2/n-type 4H-SiC MOS structure. The best quality of the SiO2/SiC interface can be achieved for the MOS structure annealed in O2 at higher temperature (800 °C) for longer time. However, higher and more uniformly distributed values of breakdown voltage were obtained for MOS structures reoxidized at temperature of 700 °C.

Direct Tunneling and Storage of Electrons in Ni Nanocrystals Embedded within MOS Structure

Recently, nanocrystal nonvolatile memory (NVM) devices using nanocrystals (NCs) have attracted great research interest. In this work, we investigated the feasibility of Ni nanocrystals embedded in metal oxide semiconductor (MOS) capacitor structure for NV

Novel ESD Protection Scheme for Testing High Voltage LDMOS

This paper presents a novel protection circuit for Electrostatic Discharge (ESD) for testing high-voltage devices using Silicon Controlled Rectifiers (SCRs). ESD related issues lead to test equipment damage, hence efficient protection techniques play a very critical role in testing high voltage devices. High-Voltage Laterally-Diffused MOSs (HV-LDMOSs) is extensively used for high voltage applications due to its advantages over other metal oxide semiconductor structures. In high voltage devices ESD protection is generally provided between the drain and source terminals. We have implemented SCRs as the ESD protection circuit for the drain connection in HV-LDMOSs. We have developed ESD stress models using conventional techniques such as human body, machine and charged device models for the high-voltage devices and implement SCRs as protection circuit in the high-voltage DIBs. Simulation has been completed to obtain the ESD stress data of the device. This ESD stress model data can be used to automate our testing process by incorporating the novel ESD protection scheme on a newly developed test software tool.

Passivation of Silicon Surfaces by Formation of Thin Silicon Oxide Films Formed by Combination of Induction-Coupled Remote Oxygen Plasma with High Pressure H2O Vapor Heat Treatment

ABSTRACTWe report formation of thin silicon oxide films on the silicon surfaces by combination of oxygen radical and high pressure H2O vapor heat treatment for passivation of silicon surfaces at a low temperature. Oxygen plasma was generated by 13.56 MHz radio frequency induction-coupled remote plasma with mixed gases of O2 and Ar at 2 sccm, 2x10-2 Pa and at a power of 50 W. Oxygen radical was produced from the plasma via a metal mesh closing plasma in the reactor. The top surfaces of 20 Wcm n-type silicon substrates with the rear surface coated by thermally grown SiO2 layers were exposed by oxygen radical from 1 to 5 min to oxidize the silicon surface. The samples were subsequently annealed with 9.0x105 Pa H2O vapor heat treatment at 260oC for 3 h. The effective minority carrier lifetime estimated using photo-induced carrier microwave absorption system in the case of 635 nm light illumination at 1.5 mW/cm2 to the top surface increased from 1.3x10-4 to 5.1x10-4s as the oxygen radical treatment duration increased from 1 to 5 min. The recombination velocity decreased from 380 to 90 cm/s. 500 kHz capacitance response with bias gate voltages characteristics of metal oxide semiconductor structure resulted in the effective oxide thicknesses (EOT) ranging from 1.3 to 1.7 nm. These results indicate a capability of thin oxide formation and effective passivation of silicon surfaces at a low temperature.

Strain Engineering of Plasma Dispersion Effect for SiGe Optical Modulators

The plasma dispersion effect and free-carrier absorption in strained SiGe are analyzed using the six-band k· <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</i> method and the Drude model. Since the hole conductivity mass of SiGe is decreased by applying compressive strain, enhancement of the plasma dispersion effect, and free-carrier absorption in strained SiGe is expected. We predict that Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> coherently grown on Si will exhibit three times higher plasma dispersion and four times higher free-carrier absorption than Si. The modulation characteristics of SiGe quantum well metal-oxide-semiconductor (MOS) optical modulators are also analyzed by technology computer-aided design simulation and finite-difference optical mode analysis. An extremely small V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">π</sub> L of 0.033 V-cm is predicted in the case of a compressively strained Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> quantum well in conjunction with a high-k gate dielectric MOS structure. The enhancement of free-carrier absorption in the SiGe high-k MOS modulator also makes in-line intensity modulation feasible and an intensity modulation efficiency of 9 dB/mm/V is predicted.

Study of density of interface states in MOS structure with ultrathin NAOS oxide

Abstract The quality of the interface region in a semiconductor device and the density of interface states (DOS) play important roles and become critical for the quality of the whole device containing ultrathin oxide films. In the present study the metal-oxide-semiconductor (MOS) structures with ultrathin SiO2 layer were prepared on Si(100) substrates by using a low temperature nitric acid oxidation of silicon (NAOS) method. Carrier confinement in the structure produces the space quantization effect important for localization of carriers in the structure and determination of the capacitance. We determined the DOS by using the theoretical capacitance of the MOS structure computed by the quantum mechanical approach. The development of the density of SiO2/Si interface states was analyzed by theoretical modeling of the C-V curves, based on the superposition of theoretical capacitance without interface states and additional capacitance corresponding to the charges trapped by the interface states. The development of the DOS distribution with the passivation procedures can be determined by this method.

Unification of three multiphonon trap-assisted tunneling mechanisms

There are three basic multiphonon trap-assisted tunneling (TAT) mechanisms in the gate leakage current of a metal-oxide-semiconductor (MOS) structure: the short-ranged trap potential, nonadiabatic interaction and electric field induced trap-band transitions. In this paper, a comparison of these three mechanisms is made for the first time in a single (Schenk’s model) MOS structure. A properly box-normalized electron wave function in the SiO2 conduction band in an electric field is used to calculate the field ionization rate of a deep neutral trap. It is found that capture and emission rates of a deep neutral trap are almost the same in the short-ranged trap potential and nonadiabatic interaction induced TAT processes, so the two mechanisms give a similar contribution to the total TAT current. The calculated TAT current and the average relaxation energy (∼1.5 eV) due to these two mechanisms are in good agreement with the experimental results. In contrast, capture and emission rates in Schenk’s model are several orders smaller. The TAT current induced by this mechanism is also much smaller and can be ignored.

InGaP/InGaAs MOS-PHEMT with a nanoscale liquid phase-oxidized InGaP dielectric

InGaP/InGaAs metal–oxide–semiconductor (MOS) pseudomorphic high-electron-mobility transistor (PHEMT) with a nanoscale liquid phase-oxidized InGaP as the gate dielectric is demonstrated. Not only does the MOS-PHEMT have the advantages of the MOS structure, but it also has high-carrier density and a high-mobility 2DEG channel. Using selective oxidation of InGaP by liquid phase oxidation, the MOS-PHEMT can be fabricated without additional recess processes. The MOS-PHEMT exhibits larger transconductance, lower gate leakage current, higher breakdown voltage, higher cut-off frequency, lower minimum noise figure, and higher power-added efficiency than does its counterpart (reference PHEMT). The interface roughness effect on the DC and RF performance of devices is also discussed.

Enhancing the lateral photovoltaic effect by coating the absorbing film on metal–oxide–semiconductor structure

By coating with a carbon film and graphene sheet (GS) on position-sensitive detectors based on the metal-oxide-semiconductor structure, sensitivity, linearity, and saturation power are significantly improved. We attribute this enhancement of absorptivity to lasers. The improvement effect of carbon film is more obvious than that of GS coating because of GS's high conductivity.

Room temperature observation of size dependent single electron tunneling ina sub-2 nm size tunable Pt nanoparticle embedded metal–oxide–semiconductorstructure

In this paper we report size dependent single electron tunneling behavior at room temperature ina metal–oxide–semiconductor structure with uniformly sized Pt nanoparticles embedded in anAl2O3 dielectric. The sub-2 nm size Pt nanoparticles sandwiched between theAl2O3 layers are deposited by a unique tilted target sputter deposition technique which producesmetal nanoparticles as small as 0.5 nm with narrow size distributions at roomtemperature. The charging behavior of these nanoparticles shows clear singleelectron tunneling peaks due to the Coulomb blockade effect. Moreover, the averagesingle electron addition energy and height of the single electron tunneling currentstrongly depend on the size of the Pt nanoparticle. These controllable single electrontunneling behaviors suggest a new route for fabrication of single electron devices.

Capacitance–Voltage Characterization of La2O3 Metal–Oxide–Semiconductor Structures on In0.53Ga0.47As Substrate with Different Surface Treatment Methods

We studied InGaAs surface treatment using hexamethyldisilazane (HMDS) vapor or (NH4)2S solution after initial oxide removal by hydrofluoric acid. The effect of each treatment on interface properties of La2O3/In0.53Ga0.47As metal–oxide–semiconductor (MOS) capacitor was evaluated. We found that HMDS surface treatment of InGaAs, followed by La2O3 deposition and forming gas annealing reduces the MOS capacitor's interface state density more effectively than (NH4)2S treatment. The comparison of the capacitance–voltage data shows that the HMDS-treated sample reaches a maximum accumulation capacitance of 2.3 µF/cm2 at 1 MHz with roughly 40% less frequency dispersion near accumulation, than the sample treated with (NH4)2S solution. These results suggest that process optimization of HMDS application could lead to further improvement of InGaAs MOS interface, thereby making it a potential routine step for InGaAs surface passivation.

Plasmonic Green Nanolaser Based on a Metal–Oxide–Semiconductor Structure

Realization of smaller and faster coherent light sources is critically important for the emerging applications in nanophotonics and information technology. Semiconductor lasers are arguably the most suitable candidate for such purposes. However, the minimum size of conventional semiconductor lasers utilizing dielectric optical cavities for sustaining laser oscillation is ultimately governed by the diffraction limit (∼(λ/2n)(3) for three-dimensional (3D) cavities, where λ is the free-space wavelength and n is the refractive index). Here, we demonstrate the 3D subdiffraction-limited laser operation in the green spectral region based on a metal-oxide-semiconductor (MOS) structure, comprising a bundle of green-emitting InGaN/GaN nanorods strongly coupled to a gold plate through a SiO(2) dielectric nanogap layer. In this plasmonic nanocavity structure, the analogue of MOS-type "nanocapacitor" in nanoelectronics leads to the confinement of the plasmonic field into a 3D mode volume of 8.0 × 10(-4) μm(3) (∼0.14(λ/2n)(3)).

Operational principles of electrochemical nanoemitter solar cells for photovoltaic and photoelectrocatalytic applications

The principle design of nanoemitter solar cells is described and their multiple applicability in photoelectrochemical solar cells that operate in the regenerative photovoltaic/photoelectrocatalytic mode as well as in solid state photovoltaics, is emphasized. For sustained operation, photoelectrochemical solar energy conversion systems have to be stabilized against corrosion processes at the reactive electrolyte interface. In the nanoemitter concept, the inclusion of passive films in the cell design allows physical stabilization of photoelectrodes. The individual steps in the preparation of photovoltaic and photoelectrocatalytic electrochemical solar cells with n- and p-type Si are described and the electronic properties of nanoemitter solar cells at the solid–liquid phase boundary are analyzed. The influence of the spatially anisotropical electrostatic potential in the nanoemitter composite structures is outlined and trajectories for the excess minority carriers are deduced that explain observed spectral properties. Routes to overcome the contact potential limitation of p-Si photocathodes for light-induced H 2 evolution are described and parameters that determine the photoelectrochemical current at the employed metallic nanoemitters which form highly local MOS (metal–oxide–semiconductor) structures are identified.

Floating Gate PMOS Dosimeters Under Bias Controlled Cycled Measurement

Floating Gate Metal Oxide Semiconductor (FG-MOS) structures, designed and fabricated in a CMOS process, were irradiated under the Bias Controlled Cycled Measurement (BCCM) novel technique conditions. Results presented in this work show the possibility of using such structures with the BCCM technique to measure ionizing radiation absorbed dose over a range of several kGy without significant loss of sensitivity. Transients observed after the bias switch are related to the evolution of the charge distribution between the floating gate and oxide traps near the semiconductor.

Measurements and microscopic model of quantum capacitance in graphene

Metal-oxide-semiconductor (MOS) structures based on graphene were fabricated with ultrathin Y2O3 films as the top gate oxide. While the quantum capacitance of graphene was measured using the MOS structure and shown to agree well with theory for ideal graphene at large channel potential, it deviates significantly from theory near the Dirac point. A general microscopic capacitance model is developed and used to describe the quantum capacitance anomaly near the Dirac point. Excellent agreement with experiment results was achieved using this model and key parameters including potential fluctuation and local carrier density fluctuation were retrieved.

Improved MOS Interface Properties of C-Face 4H-SiC by POCl&lt;sub&gt;3&lt;/sub&gt; Annealing

Metal-oxide-semiconductor (MOS) capacitors and MOS field-effect transistors (MOSFETs) were fabricated on C-face 4H-SiC with post-oxidation annealing in phosphorus- containing atmosphere. POCl3/N2 annealing at 1000 °C, which is an effective condition for Si-face, did not bring any improvement in the interface state density (Dit) for C-face due to additional oxide growth. We have developed a new process sequence suitable for C-face MOS structures. As a result, the Dit near the conduction band edge was drastically decreased by the developed process to less than 3x1011 cm−2eV−1. The field-effect mobility of C-face 4H-SiC MOSFETs was effectively increased to 37 cm2/Vs. We found that the incorporation of phosphorus atoms into the SiO2/SiC interface can improve MOSFET performance not only for the Si-face but also for the C-face.

Al 2 O 3 / GeO x / Ge gate stacks with low interface trap density fabricated by electron cyclotron resonance plasma postoxidation

An electron cyclotron resonance (ECR) plasma postoxidation method has been employed for forming Al2O3/GeOx/Ge metal-oxide-semiconductor (MOS) structures. X-ray photoelectron spectroscopy and transmission electron microscope characterizations have revealed that a GeOx layer is formed beneath the Al2O3 capping layer by exposing the Al2O3/Ge structures to ECR oxygen plasma. The interface trap density (Dit) of Au/Al2O3/GeOx/Ge MOS capacitors is found to be significantly suppressed down to lower than 1011 cm−2 eV−1. Especially, a plasma postoxidation time of as short as 10 s is sufficient to reduce Dit with maintaining the equivalent oxide thickness (EOT). As a result, the minimum Dit values and EOT of 5×1010 cm−2 eV−1 and 1.67 nm, and 6×1010 cm−2 eV−1 and 1.83 nm have been realized for Al2O3/GeOx/Ge MOS structures with p- and n-type substrates, respectively.

Metal nanocrystal memory with sol–gel derived HfO2 high-κ tunnel oxide

An all-solution processed metal–oxide–semiconductor (MOS) capacitor structure containing gold (Au) nanoparticles (NPs) within HfO2 high-κ oxide was fabricated. The ultra-thin (~10nm) HfO2 high-κ tunnel oxide layer was prepared by sol–gel process and showed good electrical properties, which were critical to superior memory property of the MOS structure. Au NPs with particle size of about 3.3nm were synthesized by chemical reduction method and then self-assembled onto HfO2 tunnel oxide. Finally, a Si/HfO2/Au NPs/HfO2 memory structure was constructed after the substrate had been covered with a sol–gel-derived HfO2 control oxide layer (~13nm). By utilizing high-quality HfO2 as tunnel oxide, the MOS structure containing Au NPs showed memory effect even at a low voltage of ±3V. Although its memory window was only 0.8V by a swapping voltage between ±5V, the MOS showed desirable retention characteristics. Therefore, we have fabricated nanocrystal memory device with sol–gel derived HfO2 high-k tunnel oxide which are attractive for low operation voltage non-volatile memory applications.