Metal Oxide Semiconductor Structures Research Articles

High performance sol–gel spin-coated titanium dioxide dielectric based MOS structures

High-κ TiO2 thin films have been fabricated using cost effective sol–gel and spin-coating technique on p-Si (100) wafer. Plasma activation process was used for better adhesion between TiO2 films and Si. The influence of annealing temperature on the structure-electrical properties of titania films were investigated in detail. Both XRD and Raman studies indicate that the anatase phase crystallizes at 400°C, retaining its structural integrity up to 1000°C. The thickness of the deposited films did not vary significantly with the annealing temperature, although the refractive index and the RMS roughness enhanced considerably, accompanied by a decrease in porosity. For electrical measurements, the films were integrated in metal-oxide-semiconductor (MOS) structure. The electrical measurements evoke a temperature dependent dielectric constant with low leakage current density. The Capacitance–voltage (C–V) characteristics of the films annealed at 400°C exhibited a high value of dielectric constant (~34). Further, frequency dependent C–V measurements showed a huge dispersion in accumulation capacitance due to the presence of TiO2/Si interface states and dielectric polarization, was found to follow power law dependence on frequency (with exponent ‘s’=0.85). A low leakage current density of 3.6×10−7A/cm2 at 1V was observed for the films annealed at 600°C. The results of structure-electrical properties suggest that the deposition of titania by wet chemical method is more attractive and cost-effective for production of high-κ materials compared to other advanced deposition techniques such as sputtering, MBE, MOCVD and ALD. The results also suggest that the high value of dielectric constant ‘κ‘ obtained at low processing temperature expands its scope as a potential dielectric layer in MOS device technology.

Tailoring the Interface between Dielectric and 4H-SiC by Ion Implantation

In this paper effects of carbon (C), silicon (Si) and nitrogen (N) implantation on the interface properties of 4H-SiC/SiO2 and the implications for 4H-SiC bipolar junction transistors (BJT) passivation are discussed. 4H-SiC epi-layer have been implanted with 12C, 14N and 28Si ion at three different doses with energies of 3, 3.5 and 6 keV, respectively, resulting in a projected range of 8 nm for the three ions. Then metal oxide semiconductor (MOS) structures with SiO2 as dielectric have been fabricated. Capacitance voltage measurements show an increase in the negative fixed charges for all the implanted samples as a function of implantation induced damage. Similarly, in the case of C and Si, the surface roughness increases as a function of dose and the mass of the ions. No reduction of Dits due to the implantations is seen for any of the ions. Furthermore, TCAD device simulations of npn bipolar junction transistors (BJT), using the interface and fixed charges extracted from CV measurements, show a way to further optimize current gain and breakdown properties for the BJT.

Dielectric engineering of Ge nanocrystal/SiO2 nanocomposite thin films with Ge ion implantation: Modeling and measurement

Abstract Ge nanocrystal (nc-Ge) embedded SiO 2 nanocomposite thin films have been synthesized with the ion implantation technique. The distribution profile of nc-Ge in the SiO 2 matrix can be tailored by varying the implantation energy and dose in the Ge ion implantation process; thus the effective dielectric constant of the nc-Ge/SiO 2 nanocomposite thin films can be engineered. The effective metal–oxide-semiconductor (MOS) capacitance of the nanocomposite thin films has been calculated using the sub-layer model and the Maxwell–Garnett effective medium approximation, taking the reduced dielectric constant corresponding to the nanometer size of nc-Ge into account. On the other hand, capacitance–voltage measurements on the MOS structures based on the nc-Ge/SiO 2 thin films have been conducted to extract the capacitance experimentally. The modeling and measurement results have shown good agreement, suggesting that the nanocomposite dielectric engineering can be easily realized through the energy- and dose-controlled Ge + implantation technique.

Effects of buffered HF cleaning on metal–oxide–semiconductor interface properties of Al2O3/InAs/GaSb structures

We studied the impact of buffered HF (BHF) cleaning on the interface properties of Al2O3/InAs/GaSb metal–oxide–semiconductor (MOS) structures fabricated by the ex-situ surface cleaning process. The Al2O3/InAs/GaSb MOS structures fabricated with BHF cleaning exhibited lower Dit values than those fabricated with sulfur passivation. In addition, the Al2O3/InAs/GaSb MOS structures fabricated with BHF cleaning were robust with respect to the MOS field-effect transistor fabrication process by using W gate metal with PMA in the 250–300 °C range.

Understanding the role of buried interface charges in a metal-oxide-semiconductor stack of Ti/Al2O3/Si using hard x-ray photoelectron spectroscopy

Hard X-ray photoelectron spectroscopy (HAXPES) analyses were carried out on metal-oxide-semiconductor (MOS) samples consisting of Si, thick and thin Al2O3, and a Ti metal cap. Using Si 1s and C 1s core levels for an energy reference, the Al 1s and Si 1s spectra were analyzed to reveal information about the location and roles of charges throughout the MOS layers. With different oxide thicknesses (2 nm and 23 nm), the depth sensitivity of HAXPES is exploited to probe different regions in the MOS structure. Post Ti deposition results indicated unexpected band alignment values between the thin and thick films, which are explained by the behavior of mobile charge within the Al2O3 layer.

SiC Nitridation by NH3 Annealing and Its Effects in MOS Capacitors with Deposited SiO2 Films

Silicon carbide (SiC) thermal nitridation followed by oxide deposition is a route to confine nitrogen at the SiO2/SiC interfacial region. To investigate its effects, incorporation of nitrogen into SiC by annealing in isotopically enriched ammonia was performed. This incorporation led mainly to silicon nitride-like formation. The observed silicon oxynitrides originated mainly from oxygen incorporation due to air exposure of samples. Metal–oxide–semiconductor structures formed by SiO2 deposition on nitrided SiC samples presented poor electrical quality, even when different postdeposition annealing conditions in argon were applied. Such results suggest that this route must be modified to allow nitrogen incorporation and avoid electrical degradation.

Effects of series and parallel resistances on the C-V characteristics of silicon-based metal oxide semiconductor (MOS) devices

This paper investigates the electrical behavior of the Al/SiO2/Si MOS structure. We have used the complex admittance method to develop an analytical model of total capacitance applied to our proposed equivalent circuit. The charge density, surface potential, semiconductor capacitance, flatband and threshold voltages have been determined by resolving the Poisson transport equations. This modeling is used to predict in particular the effects of frequency, parallel and series resistance on the capacitance-voltage characteristic. Results show that the variation of both frequency and parallel resistance causes strong dispersion of the C-V curves in the inversion regime. It also reveals that the series resistance influences the shape of C-V curves essentially in accumulation and inversion modes. A significant decrease of the accumulation capacitance is observed when Rs increases in the range 200–50000 Ω. The degradation of the C-V magnitude is found to be more pronounced when the series resistance depends on the substrate doping density. When Rs varies in the range 100 Ω–50 kΩ, it shows a decrease in the flatband voltage from −1.40 to −1.26 V and an increase in the threshold voltage negatively from −0.28 to −0.74 V, respectively. Good agreement has been observed between simulated and measured C-V curves obtained at high frequency. This study is necessary to control the adverse effects that disrupt the operation of the MOS structure in different regimes and optimizes the efficiency of such electronic device before manufacturing.

Electrical properties of spin coated ultrathin titanium oxide films on GaAs

In recent years, ultrathin (<50 nm) metal oxide films have been being extensively studied as high-k dielectrics for future metal oxide semiconductor (MOS) technology. This paper discusses deposition of ultrathin TiO2 films (∼10 nm) on GaAs substrates (one sulfur-passivated, another unpassivated) by spin coating technique. The sulfur passivation is done to reduce the surface states of GaAs substrate. After annealing at 400 °C in a nitrogen environment, the TiO2 films are found to be polycrystalline in nature with rutile phase. The TiO2 films exhibit consistent grain size of 10–20 nm with thickness around 10–12 nm. Dielectric constants of the films are found to be 65.4 and 47.1 corresponding to S-passivated and unpassivated substrates, respectively. Corresponding threshold voltages of the MOS structures are measured to be −0.1 V to −0.3 V for the S-passivated and unpassivated samples, respectively. The S-passivated TiO2 film showed improved (lower) leakage current density (5.3 × 10−4 A cm−2 at 3 V) compared to the unpassivated film (1.8 × 10−3 A/cm2 at 3 V). Dielectric breakdown-field of the TiO2 films on S-passivated and unpassivated GaAs samples are found to be 8.4 MV cm−1 and 7.2 MV cm−1 respectively.

Interfacial and electrical properties of InGaAs metal-oxide-semiconductor capacitor with TiON/TaON multilayer composite gate dielectric

InGaAs metal-oxide-semiconductor (MOS) capacitors with composite gate dielectric consisting of Ti-based oxynitride (TiON)/Ta-based oxynitride (TaON) multilayer are fabricated by RF sputtering. The interfacial and electrical properties of the TiON/TaON/InGaAs and TaON/TiON/InGaAs MOS structures are investigated and compared. Experimental results show that the former exhibits lower interface-state density (1.0 × 1012 cm−2 eV−1 at midgap), smaller gate leakage current (9.5 × 10−5 A/cm2 at a gate voltage of 2 V), larger equivalent dielectric constant (19.8), and higher reliability under electrical stress than the latter. The involved mechanism lies in the fact that the ultrathin TaON interlayer deposited on the sulfur-passivated InGaAs surface can effectively reduce the defective states and thus unpin the Femi level at the TaON/InGaAs interface, improving the electrical properties of the device.

Impedance analysis of Al2O3/H-terminated diamond metal-oxide-semiconductor structures

Impedance spectroscopy (IS) analysis is carried out to investigate the electrical properties of the metal-oxide-semiconductor (MOS) structure fabricated on hydrogen-terminated single crystal diamond. The low-temperature atomic layer deposition Al2O3 is employed as the insulator in the MOS structure. By numerically analysing the impedance of the MOS structure at various biases, the equivalent circuit of the diamond MOS structure is derived, which is composed of two parallel capacitive and resistance pairs, in series connection with both resistance and inductance. The two capacitive components are resulted from the insulator, the hydrogenated-diamond surface, and their interface. The physical parameters such as the insulator capacitance are obtained, circumventing the series resistance and inductance effect. By comparing the IS and capacitance-voltage measurements, the frequency dispersion of the capacitance-voltage characteristic is discussed.

Interface/border trap characterization of Al2O3/AlN/GaN metal-oxide-semiconductor structures with an AlN interfacial layer

We report the interface characterization of Al2O3/AlN/GaN MOS (metal-oxide-semiconductor) structures with an AlN interfacial layer. A thin monocrystal-like interfacial layer (AlN) is formed at the Al2O3/GaN to effectively block oxygen from the GaN surface and prevent the formation of detrimental Ga-O bonds. The suppression of Ga-O bonds is validated by X-ray photoelectron spectroscopy of the critical interface. Frequency-dispersion in C-V characteristics has been significantly reduced, owing to improved interface quality. Furthermore, using the conventional conductance method suitable for extracting the interface trap density Dit in MOS structures, Dit in the device with AlN was determined to be in the range of 1011–1012 eV−1 cm−2, showing one order of magnitude lower than that without AlN. Border traps near the gate-dielectric/GaN interface were identified and shown to be suppressed by the AlN interfacial layer as well.

Interface Properties of 4H-SiC (&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$11\bar {2}0$ &lt;/tex-math&gt;&lt;/inline-formula&gt;) and (&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$1\bar {1}00$ &lt;/tex-math&gt;&lt;/inline-formula&gt;) MOS Structures Annealed in NO

Interface properties of 4H-SiC (112̅0) and (11̅00) walls, the absence of junction FET resistance, and the higher metal-oxide-semiconductor (MOS) structures annealed in nitric oxide are characterized by conductance, high-low, and C-ψ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</sub> methods. Compared with 4H-SiC (0001) MOS structures, generation of very fast interface states by nitridation is much smaller in 4H-SiC (112̅0) and (11̅00). The effective mobility of planar MOSFETs fabricated on Al+-implanted p-body doped to 1×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">17</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> is 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs on (11̅00), 92 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs on (112̅0), and 20 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs on (0001). The mobility-limiting factors are discussed on the basis of experimental results. The high channel mobilities for (112̅0) and (11̅00) MOSFETs can be correlated with the lower density of fast interface states generated by nitridation.

Effects of HCl treatment and predeposition vacuum annealing on Al2O3/GaSb/GaAs metal–oxide–semiconductor structures

The effects of HCl treatment and predeposition vacuum annealing (VA) on n-type GaSb/GaAs metal–oxide–semiconductor (MOS) structures with the atomic layer deposition (ALD) of Al2O3 dielectrics are studied. We obtained MOS structures with good Fermi level modulation by HCl treatment prior to the deposition of Al2O3. From X-ray photoelectron spectroscopy (XPS) analysis, we found that the Ga2O3 content increases during the Al2O3 deposition, whereas the amounts of Sb components are reduced. The excess growth of Ga2O3 is inhibited by the reductions in the amounts of Sb components by the HCl treatment. Further reductions in the amounts of Sb components are observed following predeposition VA, indicating a lower density of states (Dit). However, the frequency dispersion in the capacitance–voltage (C–V) characteristics increases with predeposition VA at higher temperatures.

Investigation of Pd/TiO2/Si MIS capacitor as hydrogen sensor

Purpose – This paper aims to investigate the gas-sensing capability of Pd/TiO2/Si MIS capacitor using capacitance versus gate voltage (C-V) response as a function of hydrogen gas concentration varying from 0.1 to 2 ppm at 300 kHz frequency. Design/methodology/approach – The objective is to fabricate a metal–insulator–semiconductor (MIS) capacitor sensor based on TiO2-thin-film insulator deposited by sol-gel spin-coating process. Gas-sensing signal derived on exposure to hydrogen with concentration varying from 0.1 to 2 ppm at different operating temperatures (room temperature to 1,500°C) was measured as variation in flat-band voltage in C-V characteristics of the MIS capacitor. Findings – High sensitivity of the sensor is attributed to the large change of interface state charges because of the large surface-to-volume ratio of the nano-structured TiO2. The values of response time as well as the recovery time have also been estimated and are found to be comparable to that observed in the case of conventional Metal Oxide Semiconductor (MOS) structure. Research limitations/implications – The use of Si substrate restricts the performance of gas sensors to 200°C, as the Si substrate begins to show conductive nature. Originality/value – This paper deals with an MIS capacitor gas sensor which replaces conventional insulating material by TiO2 and uses a high-quality fabrication procedure for controlled growth of novel surface structure.

A compact plasmonic MOS-based 2×2 electro-optic switch

Abstract We report on a three-waveguide electro-optic switch for compact photonic integrated circuits and data routing applications. The device features a plasmonic metal-oxide-semiconductor (MOS) mode for enhanced light-matter-interactions. The switching mechanism originates from a capacitor-like design where the refractive index of the active medium, indium-tin-oxide, is altered via shifting the plasma frequency due to carrier accumulation inside the waveguide-based MOS structure. This light manipulation mechanism controls the transmission direction of transverse magnetic polarized light into either a CROSS or BAR waveguide port. The extinction ratio of 18 (7) dB for the CROSS (BAR) state, respectively, is achieved via a gating voltage bias. The ultrafast broadband fJ/bit device allows for seamless integration with silicon-on-insulator platforms for low-cost manufacturing.

Memory characteristics and tunneling mechanism of Pt nano-crystals embedded in HfAlOx films for nonvolatile flash memory devices

A non-volatile flash memory device based on metal oxide semiconductor (MOS) capacitor structure has been fabricated using platinum nano-crystals(Pt–NCs) as storage units embedded in HfAlOx high-k tunneling layers. Its memory characteristics and tunneling mechanism are characterized by capacitance–voltage(C–V) and flat-band voltage-time(ΔVFB-T) measurements. A 6.5V flat-band voltage (memory window) corresponding to the stored charge density of 2.29 × 1013cm−2 and about 88% stored electron reserved after apply ±8V program or erase voltage for 105s at high frequency of 1 MHz was demonstrated. Investigation of leakage current–voltage(J–V) indicated that defects-enhanced Pool-Frenkel tunneling plays an important role in the tunneling mechanism for the storage charges. Hence, the Pt–NCs and HfAlOx based MOS structure has a promising application in non-volatile flash memory devices.

Electrical properties of ultrathin titanium dioxide films on silicon

Ultrathin (&amp;lt;50 nm) titanium dioxide (TiO2) films are being widely investigated as high-k dielectrics for future metal oxide semiconductor (MOS) technology. In this paper, ultrathin TiO2 films (∼20 nm) were deposited on silicon substrates by sputtering technique and subsequently annealed at 800 °C in oxygen environment for different durations (15–60 min). The annealed films were polycrystalline in nature with rutile phase. The value of dielectric constant was found to be 32–60 at 1 kHz measurement frequency. Threshold voltages of the MOS structures were found to vary from −0.1 to −0.5 V with the duration of annealing. Leakage current density (1 × 10−2–1 × 10−8 A/cm2 at 1 V) and dielectric breakdown fields (8.15–9.8 MV/cm) were observed to improve with annealing time.

Polarization of Bi2Te3 thin film in a floating-gate capacitor structure

Metal-Oxide-Semiconductor (MOS) capacitors with Bi2Te3 thin film sandwiched and embedded inside the oxide layer have been fabricated and studied. The capacitors exhibit ferroelectric-like hysteresis which is a result of the robust, reversible polarization of the Bi2Te3 thin film while the gate voltage sweeps. The temperature-dependent capacitance measurement indicates that the activation energy is about 0.33 eV for separating the electron and hole pairs in the bulk of Bi2Te3, and driving them to either the top or bottom surface of the thin film. Because of the fast polarization speed, potentially excellent endurance, and the complementary metal–oxide–semiconductor compatibility, the Bi2Te3 embedded MOS structures are very interesting for memory application.

Integration of atomic layer deposited high-k dielectrics on GaSb via hydrogen plasma exposure

In this letter we report the efficacy of a hydrogen plasma pretreatment for integrating atomic layer deposited (ALD) high-k dielectric stacks with device-quality p-type GaSb(001) epitaxial layers. Molecular beam eptiaxy-grown GaSb surfaces were subjected to a 30 minute H2/Ar plasma treatment and subsequently removed to air. High-k HfO2 and Al2O3/HfO2 bilayer insulating films were then deposited via ALD and samples were processed into standard metal-oxide-semiconductor (MOS) capacitors. The quality of the semiconductor/dielectric interface was probed by current-voltage and variable-frequency admittance measurements. Measurement results indicate that the H2-plamsa pretreatment leads to a low density of interface states nearly independent of the deposited dielectric material, suggesting that pre-deposition H2-plasma exposure, coupled with ALD of high-k dielectrics, may provide an effective means for achieving high-quality GaSb MOS structures for advanced Sb-based digital and analog electronics.

Surface photovoltage method for the quality control of silicon epitaxial layers on sapphire

The surface photovoltage method is used to study “silicon-on-sapphire” epitaxial layers with a thickness of 0.3–0.6 μm, which are used to fabricate p-channel MOS (metal—oxide-semiconductor) transistors with improved radiation hardness. It is shown that the manner in which the photoconductivity of the epitaxial layer decays after the end of a light pulse generated by a light-emitting diode (wavelength ∼400 nm) strongly depends on the density of structural defects in the bulk of the structure. This enables control over how a “silicon-on-sapphire” structure is formed to provide the manufacturing of MOS structures with optimal operating characteristics.