Metal Oxide Semiconductor Structures Research Articles

Size and density controlled Ag nanocluster embedded MOS structure for memory applications

Metal-nanoclusters (NC), deposited by magnetron-based nanocluster source coupled with quadrupole mass filter (QMF) assembly having independent control over their size and density, are used in fabricating NC-based non-volatile memory (NVM) devices. The effect of diameter and density on the NVM charge storage characteristics are presented where Ag is used as the metal NC. The Ag-NC, sandwiched between HfO2 tunnel and control oxides, is deposited by using the combination of the above two instruments. No annealing is performed at any stage of the device fabrication. The largest hysteresis loop area in the capacitance-voltage (C−V) characteristics of metal-oxide-semiconductor (MOS) characteristics is observed for a cluster density of 1×1011cm−2. Further, an NC size dependent hysteresis loop area is observed with the MOS devices where the NC diameter is varied from 3 to 1.5nm keeping the NC density at 1×1011cm−2. The device performance is found to be improved with a reduction of the NC size and shows its best with the NC diameter of 1.5nm. The storage time of the NVM devices also increases with the decrease in the NC diameter and exhibits their best performances for the NCs with a diameter of 1.5nm.

Applicability of MOS structures in monitoring catalytic properties, as exemplified for monolayer-iron-oxide-coated porous platinum films

Metal Oxide Semiconductor (MOS) capacitor devices comprised of monolayer iron oxide-coated as well as non-coated polycrystalline Pt deposited on oxidized silicon carbide substrates have been fabricated and their usefulness as realistic model systems in catalyst studies/development was evaluated. The CO oxidation characteristics of both iron oxide- and non-coated Pt catalysts were investigated using mass spectrometry, monitoring the carbon dioxide production rate for different combinations of carbon monoxide (CO) and oxygen concentrations at various temperatures. Additionally, the output capacitance of the MOS model catalysts was recorded for each individual CO oxidation activity. A low-temperature shift in CO oxidation characteristics for the monolayer-coated compared to the non-coated Pt catalysts was observed, similar to that previously reported for monolayer iron oxide grown on single-crystalline Pt substrates. A strong correlation between the output capacitance of the MOS structures and the CO oxidation characteristics was found for both monolayer- and non-coated model catalysts. Furthermore, the devices exhibit retained MOS electrical output and CO oxidation characteristics as well as an unaffected catalyst surface composition, as confirmed by photoelectron spectroscopy, even after 200h of continuous model catalyst operation. In addition to the implications on practical applicability of monolayer iron oxide coating on widely used polycrystalline Pt films in real-world catalysts and sensors, the findings also point to new possibilities regarding the use of MOS model systems for in situ characterization, high-throughput screening, and tailoring of e.g. catalyst- and fuel-cell-electrode materials for specific applications.

Distribution and coverage of 40 nm gold nano-particles on aluminum and hafnium oxide using electrophoretic method and fabricated MOS structures

In this paper, electrophoretic method (EPD) is used to deposit 40nm gold nano-particles (GNPs) on atomic layer deposited (ALD) grown oxides. Ultra-High Resolution Scanning Electron Microscopy (HRSEM) has been used to study the distribution of gold nano-particles on both Al2O3 and HfO2 thin films as a function of dipping time. The results show better distribution and mechanical adhesion of GNPs on top of HfO2 compared to Al2O3. Additionally, metal-oxide-semiconductor (MOS) structures with GNPs embedded within the HfO2 layers are fabricated. The distribution and coverage of the GNPs are analyzed using hysteresis loop of capacitance-voltage measurements at (1.0MHz) and by quantifying the threshold voltage shift (ΔVt). Moreover, the distribution of the GNPs as function of dipping time is discussed in terms of the measured ΔVt. The results show an increase in ΔVt with longer dipping time followed by a drop in the ΔVt. Moreover, the Vt shift vs. dipping time indicates changes in the electrophoretic mobility behavior and the final distribution of GNPs on the surface of the HfO2.

Investigation of surface and interface properties of RF sputtered calcium copper titanate thin films on silicon substrate

Structural and electrical properties of RF sputtered Calcium copper titanate (CCTO) thin films have been investigated. CCTO thin films were sputtered on p-type silicon (100) substrate by varying deposition pressure from 2.5 × 10−3 to 1 × 10−2 mbar without using platinum buffer layer. Post deposition annealing of all the samples were carried out at 950 °C. A correlation between morphological and electrical properties of the CCTO films was established with the variation of deposition pressure. The evolution of polycrystalline structure of the CCTO thin films was confirmed by XRD studies. The characteristic FTIR absorption peaks in the range of 400–700 cm−1 depicted the formation of CCTO for all the samples. The films grown at higher pressure have irregular grains with the evolution of (310) peak. Electrical properties of the dielectric films were investigated by fabricating Al/CCTO/Si metal oxide semiconductor structure. The electrical properties of the CCTO films were found to be deteriorated at higher sputtering pressure. Thin films, deposited at 5 × 10−3 mbar, possess higher dielectric constant, lower charge density and also lower leakage current.

Controlling the defects and transition layer in SiO2 films grown on 4H-SiC via direct plasma-assisted oxidation.

The structural stability and electrical performance of SiO2 grown on SiC via direct plasma-assisted oxidation were investigated. To investigate the changes in the electronic structure and electrical characteristics caused by the interfacial reaction between the SiO2 film (thickness ~5 nm) and SiC, X-ray photoelectron spectroscopy (XPS), X-ray absorption spectroscopy (XAS), density functional theory (DFT) calculations, and electrical measurements were performed. The SiO2 films grown via direct plasma-assisted oxidation at room temperature for 300s exhibited significantly decreased concentrations of silicon oxycarbides (SiOxCy) in the transition layer compared to that of conventionally grown (i.e., thermally grown) SiO2 films. Moreover, the plasma-assisted SiO2 films exhibited enhanced electrical characteristics, such as reduced frequency dispersion, hysteresis, and interface trap density (Dit ≈ 1011 cm−2 · eV−1). In particular, stress induced leakage current (SILC) characteristics showed that the generation of defect states can be dramatically suppressed in metal oxide semiconductor (MOS) structures with plasma-assisted oxide layer due to the formation of stable Si-O bonds and the reduced concentrations of SiOxCy species defect states in the transition layer. That is, energetically stable interfacial states of high quality SiO2 on SiC can be obtained by the controlling the formation of SiOxCy through the highly reactive direct plasma-assisted oxidation process.

Correct extraction of frequency dispersion in accumulation capacitance in InGaAs metal-insulator-semiconductor devices

The anomalous frequency dispersion of the accumulation capacitance, i.e. an increase in the accumulation capacitance at high frequencies, of Pt/Al2O3/InGaAs metal-oxide-semiconductor (MOS) capacitors was investigated in this study. The anomalous frequency dispersion can be attributed to the considerable effects of parasitic inductance at high frequencies. The effects of parasitic inductance were effectively suppressed by decreasing the capacitor area without changing the MOS structure. This suggests that a smaller capacitor area should be used to precisely characterize the capacitance-voltage behavior of InGaAs-based MOS devices.

Effect of nitrogen incorporation into Al-based gate insulators in AlON/AlGaN/GaN metal–oxide–semiconductor structures

The superior physical and electrical properties of aluminum oxynitride (AlON) gate dielectrics on AlGaN/GaN substrates in terms of thermal stability, reliability, and interface quality were demonstrated by direct AlON deposition and subsequent annealing. Nitrogen incorporation into alumina was proven to be beneficial both for suppressing intermixing at the insulator/AlGaN interface and reducing the number of electrical defects in Al2O3 films. Consequently, we achieved high-quality AlON/AlGaN/GaN metal–oxide–semiconductor capacitors with improved stability against charge injection and a reduced interface state density as low as 1.2 × 1011 cm−2 eV−1. The impact of nitrogen incorporation into the insulator will be discussed on the basis of experimental findings.

Photon-Induced Negative Capacitance in Metal Oxide Semiconductor Structures

Design and fabrication of photon-induced negative capacitance is presented. The capacitor is implemented using Silicon on Insulator Metal Oxide Semiconductor platform, where the gate dielectric is made of a nonferroelectric material. Operating at room temperature, when the device is illuminated, in depletion mode the total capacitance grows in magnitude to values larger than the geometrical capacitance. We believe this is caused by the trap states existing at the interface of dielectric and semiconductor layers, and present the supporting modeling results. Using our model, we investigate the role of the trap density and light intensity, as well as the device geometry such as gate-ground position and the thickness of the silicon layer. Our model shows the depletion capacitance can grow to values more than three times larger than the geometrical capacitance.

Carrier Selective Contacts Design for Efficient Photocatalytic Water Reduction

2-photon tandem device structures that consist of a wide band gap and narrow band gap photoabsorber can maximize photoelectrolysis efficiency since their I-V characteristics match well with that needed for photoelectrolysis [1]. In the case of the narrow band gap (Eg ) material, recent theoretical work has shown that Si has a suitable Eg for the bottom cell of tandem water splitting device [2]. Since current performance of Si PEC cells lag far behind the theoretical limit [3], the need for a different approach increases. Up to now, tremendous efforts have been made to improve the performance of Si-based photocathodes [4-6]. One approach the solar cells industry uses to increase performance is to use metal-oxide-semiconductor (MOS) carrier-selective contacts due to their efficient carrier transport and low recombination [5,6]. However, very little work has been done studying photocatalytic hydrogen evolution reaction (HER) with the MOS structure. Moreover, there has been no detailed report on energy band level analysis to understand how the carriers can be selectively injected.In this work we demonstrate μc-Si/SiO2/p-Si structure (see Figure 1) to both front and back contacts which provide interface passivation and selective injection of minority and majority carrier to solid/liquid interface and back contact, respectively. A transparent TiO2 is placed above the highly doped μc-Si thin film as a conducting protection layer, and then Pt nanoparticles were drop-casted on the samples for photocatalytic HER in 1M HClO4. Using thin film degenerately doped Si as a metallic layer has been employed in recent state-of-art MOS based PV cells [7], but combination with TiO2 as a conducting protection layer for PEC hydrogen production has not been shown so far. Moreover, the details working principles based on the band energy analysis are outlined to understand how the carriers can be injected selectively and transferred to solid/liquid interface in PEC system.1. B. Seger, I.E. Castelli, P.C.K. Vesborg, K.W. Jacobsen, O. Hansen, I. Chorkendorff, Energy Environ. Sci. 7 (2014) 2397–2413. 2. A.B. Laursen, S. Kegnæs, S. Dahl, I. Chorkendorff, Energy Environ. Sci. 5 (2012) 5577. 3. W. Shockley, H.J. Queisser, J. Appl. Phys. 32 (1961) 510–519. 4. D. Bae, T. Pedersen, B. Seger, M. Malizia, A. Kuznetsov, O. Hansen, I. Chorkendorff, P.C.K. Vesborg, Energy Environ. Sci. 8 (2015) 650–660. 5. D. V Esposito, I. Levin, T.P. Moffat, A.A. Talin, Nat. Mater. 12 (2013) 562–8. 6. A.G. Scheuermann, J.P. Lawrence, K.W. Kemp, T. Ito, A. Walsh, C.E.D. Chidsey, P.K. Hurley, P.C. McIntyre, Nat. Mater. (2015) 1–8. 7. F. Feldmann, M. Simon, M. Bivour, C. Reichel, M. Hermle, S.W. Glunz, Sol. Energy Mater. Sol. Cells. 131 (2014) 100–104. Figure 1

Ferroelectric, stacked gate FETs: A prospective for planar CMOS with reduced leakage current and Sub-kT/q subthreshold swing

The planar silicon-on-insulator (SOI) based metal-oxide semiconductor (MOS) structure has been at the center of attention of researchers who are attempting to extend its scalability. This study presents an analysis of ferroelectric MOS field effect transis-tors (Fe-MOSFETs) based on the surface potential, threshold voltage, subthreshold swing, leakage current, ON current and electron temperature. In addition, the electro-static integrity (EI) factor and the threshold-voltage-to-swing ratio for Fe-MOSFETs were estimated and compared with those of conventional, high-k and double-gate (DG) MOSFETs. The analysis shows that the Fe-MOSFET is able to enhance the scalability and fulfil the expectation of researchers studying planar complementary MOS (CMOS) devices.

Capacitance-voltage characteristics of Si and Ge nanomembrane based flexible metal-oxide-semiconductor devices under bending conditions

Metal-oxide-semiconductor (MOS) device is the basic building block for field effect transistors (FET). The majority of thin-film transistors (TFTs) are FETs. When MOSFET are mechanically bent, the MOS structure will be inevitably subject to mechanical strain. In this paper, flexible MOS devices using single crystalline Silicon (Si) and Germanium (Ge) nanomembranes (NM) with SiO2, SiO, and Al2O3 dielectric layers are fabricated on a plastic substrate. The relationships between semiconductor nanomembranes and various oxide materials are carefully investigated under tensile/compressive strain. The flatband voltage, threshold voltage, and effective charge density in various MOS combinations revealed that Si NM−SiO2 configuration shows the best interface charge behavior, while Ge NM−Al2O3 shows the worst. This investigation of flexible MOS devices can help us understand the impact of charges in the active region of the flexible TFTs and capacitance changes under the tensile/compressive strains on the change in electrical characteristics in flexible NM based TFTs.

Enhanced saturation current sensitivities to charge trapping and illumination in MOS tunnel diode by inserting metal in gate dielectric

The enlarged two-state phenomenon in the current–voltage (I–V) characteristic of metal–oxide–semiconductor (MOS) tunnel diode (TD) after negative/positive constant voltage stress (negative/positive CVS) was investigated. It was found that the reverse saturation tunnel current of MOS TD is proportional to the Schottky barrier height of holes, which is determined by the intensity of fringing field (FF) at device edge. With the aid of high permittivity dielectric and screening effect by embedded metal in the MOS structure, the FF was enhanced, which was confirmed by TCAD simulations. Because of the FF enhancement, after proper electrical treatments of voltage stressing, the intensified quantity of electron trapping/de-trapping was found at device edge, which augmented the modulation of Schottky barrier height of holes. As a result, much variation of reverse saturation tunnel current was exhibited, and hence, the enlarged two-state behavior was achieved. The endurance characteristics were also demonstrated to show that the trapped electrons are more stable in the MOS structure with embedded aluminum. Moreover, benefited from FF enhancement, the enlarged photosensitivity of the I–V characteristics of the sample with high permittivity dielectric and embedded aluminum was obtained. The mechanisms of the enlarged split of current behaviors after suitable CVS and illumination treatments are also discussed for these observations.

Kinetic Monte Carlo Simulations of Defects in Anatase Titanium Dioxide

Anatase titanium dioxide is a highly promising material for memristors and photocatalysis. Multiple electronic transport processes are known to be influenced by defects in nanoscale anatase. Hence, in this study, we examine charge transport due to defects with respect to the fabrication of nanometer-thin TiO2 films via kinetic Monte Carlo (kMC). A compact kMC model for metal–oxide–semiconductor (MOS) and metal–oxide–metal (MOM) structures comprising TiO2 was parametrized by the electronic properties of TiO2 in agreement with the literature, in particular, spectroscopic studies and DFT calculations on defects in anatase. kMC simulations of MOS structures were refined, for the first time, by separate drift-diffusion simulations on the band bending in p+-Si substrates as well as by barrier heights adjusted for the Fermi level pinning effect. Referring to the impact of specific TiO2 film growth methods and postgrowth treatments on the parameters for defect energies in particular, electrical jV characteristics...

Determination of Fowler–Nordheim tunneling parameters in Metal–Oxide–Semiconductor structure including oxide field correction using a vertical optimization method

Current conduction mechanisms through a Metal–Oxide–Semiconductor structure are characterized via Fowler–Nordheim (FN) plots. The extraction of the FN parameters like the electron/hole effective mass in oxide mox and in semiconductor msc, the barrier height at the semiconductor–oxide interface ϕB, and the correction oxide voltage Vcorr for a MOS structure is made using a vertical optimization process on the current density without any assumption about ϕB or mox. An excellent agreement is obtained between the FN plots calculated with the FN parameters extracted using a vertical optimization process with the experimental one.

Lateral Non-Uniformity Reduction by Compensatory Metal Embedded in MOS Structure with Ultra-Thin Anodic Oxide

In order to reduce the degradation caused by lateral non-uniformity (LNU) of gate oxides in metal-oxide-semiconductor (MOS) devices, a method to ameliorate the lateral oxide uniformity was proposed. By adopting the anodic oxidation compensation (ANO-compensation) technique to compensate the embedded aluminum layer, significant uniformity improvements were found in capacitance per unit area-voltage (C’-V) and current density-voltage (J-V) characteristics, and the percentage dispersions of capacitance per unit area and current density in accumulation regime also give the support to uniformity improvement. Besides, the outcomes of reliability tests also evidence that the LNU is reduced. Hence, with the advantages of superior oxide uniformity, the enhanced response in inversion capacitance was observed. At last, nitrate solution is used for validating the advantage of anodic oxidation compensation, and the J-V and C-V characteristics show that anodic oxidation compensation is necessary for fabricating reliable MOS-based devices.

Memcapacitive Characteristics of Metal-Oxide-Semiconductor Capacitor Structures by Compositional Redistribution

The memcapacitive characteristics in metal-oxide-semiconductor (MOS) capacitor structures consisting of reactive electrode (Mo, Al) and hafnium oxide (HfOX) on n-type Si and indium-gallium-zinc-oxide (IGZO) semiconductor were investigated. The capacitance-voltage (C-V) curves exhibited sequentially changing capacitance as repeating the voltage sweeps in an analog fashion. The saturation capacitance was decreased as repeatedly applying +V, while the depletion capacitance was barely changed at repeated –V application. The capacitance-time (C-t) curves disclosed the same tendency of capacitance change. On the other hand, the MOS structure with inert electrode (Pt) did not show the capacitance change. These memcapacitive behaviors were induced by the migration of oxygen ions between reactive electrodes (Mo, Al) and HfOX, modulating the permittivity and effective capacitor area. These results demonstrated the memcapacitive characteristics in MOS structure through voltage-driven oxygen migration, which could be applied to memory, logic, and neuromorphic devices.

Integrated low‐temperature process for the fabrication of amorphous Si nanoparticles embedded in Al2O3 for non‐volatile memory application

A new low‐temperature, integrated fabrication process for multi layers of silicon nanoparticles (Si‐NPs) embedded in amorphous Al2O3 is presented. For this, a non‐thermal low‐pressure inductively coupled plasma process (LPICP) for Si‐NPs and thermal atomic layer deposition (ALD) of Al2O3 are combined. Storage characteristics of metal–oxide–semiconductor (MOS) structures are studied for non‐volatile memory application. The influence of typical fixed oxide charges in Al2O3 on the programming process and retention is investigated.HAADF and EDX images of MOS structure with five layers of silicon nanoparticles.

Slow response in gate current–voltage characteristics of metal–oxide–semiconductor structures on the 4H-SiC face

We have investigated the gate current–voltage (Ig–Vg) characteristics of n-channel metal–oxide–semiconductor field-effect transistors (MOSFETs) and p-MOS capacitors on the 4H-SiC face. The gate current response to a change in gate voltage has a very slow part, which has been considered to be due to slow traps in the oxide near the SiO2–SiC interface. However, we found that the slow response can be explained by fast interface traps if the traps have a relatively large concentration. Carrier injection into the interface traps results in a change in the surface potential, and this suppresses the further injection of carriers. This new model can explain many electrical properties such as the constant-current behavior in the Ig–Vg characteristics, which was confirmed by one-dimensional (1D) device simulation. According to this model, the interface traps will not be occupied up to the surface Fermi level within the general time scale of the measurement. In spite of the arguments described above, slow traps also probably exist near the interface between SiO2 and SiC.

Interface state density of SiO2/p-type 4H-SiC (0001), (112¯), (11¯00) metal-oxide-semiconductor structures characterized by low-temperature subthreshold slopes

Interface properties of heavily Al-doped 4H-SiC (0001) (Si-face), (112¯0) (a-face), and (11¯00) (m-face) metal-oxide-semiconductor (MOS) structures were characterized from the low-temperature gate characteristics of metal-oxide-semiconductor field-effect transistors (MOSFETs). From low-temperature subthreshold slopes, interface state density (Dit) at very shallow energy levels (ET) near the conduction band edge (Ec) was evaluated. We discovered that the Dit near Ec (Ec− 0.01 eV < ET < Ec) increases in MOS structures with higher Al doping density for every crystal face (Si-, a-, and m-face). Linear correlation is observed between the channel mobility and Dit near Ec, and we concluded that the mobility drop observed in heavily doped MOSFETs is mainly caused by the increase of Dit near Ec.

The important contribution of photo-generated charges to the silicon nanocrystals photo-charging/discharging-response time at room temperature in MOS-photodetectors

The results are reported of a detailed investigation into the photogenerated changes that occur in the capacitance–voltage (C–V) characteristics of Metal-Oxide-Semiconductor (MOS) photodetector, having a silicon nanocrystals (Si-ncs) embedded in SiOx=1.5 tunnel oxide layers. In order to study the influence of photon energy on charging/discharging photo-response of nanocrystal-based MOS structures, we have examined photo-capacitance-voltage (photo-CV) measurements at both light intensities 45 μW and 75 μW and wavelengths 436 nm and 595 nm. The photo-CV measurements indicate the important contribution of photo-generated charges to the charging/discharging mechanism. The (Si-ncs) charging/discharging photo-response time is evaluated to be 300 s at wavelength of 595 nm for 75 μW optical power at room temperature. This response time is influenced by the photogenerated-holes lifetime in the Si-ncs.