Low Drain Voltage Research Articles

TCAD analysis of conditions for DIBL parameter misestimation in cryogenic MOSFETs

The study aimed to theoretically investigate the transfer characteristics of MOSFETs at cryogenic temperatures to elucidate the experimental conditions affecting the accurate estimation of the drain-induced barrier lowering (DIBL) parameter. Our Technology Computer Aided Design (TCAD) simulation revealed that MOSFETs featuring an underlap between the gate and source/drain edges experience a significant shift in threshold voltage (V t) in the low drain voltage (V d) region, which causes the misestimation of the DIBL parameter. This V t change is due to a notable increase in carrier concentration within the underlap region. To mitigate misestimation in such underlap devices, confirming the dependence of the DIBL parameter on the linear region of V d serves as an effective method to ensure accurate estimation.

Carbohydrate-based block copolymers with sub-10 nm face-centered cubic nanostructures for low-power-consuming and ultraviolet light-triggered synaptic phototransistors

Addressing environmental concerns and producing sustainable and environmentally friendly electronic devices with low power consumption poses a significant challenge. This study introduces phototransistor devices employing morphologically controlled block copolymers based on maltotriose, maltoheptaose, and β-cyclodextrin as polymer electrets. Ordered self-assembled morphologies can be achieved by utilizing microwave radiation for rapid annealing (within 5 s) with optimized annealing conditions. Herein, face-centered cubic (FCC), vertical, and mixed cylindrical nanostructures are reported. The resulting well-defined morphologies play a pivotal role in enhancing the electron-trapping capability of the block copolymers and facilitating charge carrier transport between the electret and semiconducting layers. Consequently, the phototransistor memory manifests exceptional performance, featuring stability and endurance. Intriguingly, the cavity of β-cyclodextrin provides a stable environment for the trapped charges, leading to a larger memory window than other block copolymers. On the other hand, a device consisting of MT-b-PS exhibited superior current contrast exceeding 106 even under a low drain voltage of −1 V, attributed to sub-10 nm FCC nanostructures. Furthermore, this phototransistor device successfully emulated the synaptic functions of sensing, learning, and short- and long-term memory in the human brain, along with a low energy consumption of 0.312 fJ. Hence, this report opens the pathways for developing promising bio-based electronic devices.

A novel ballistic model for the subthreshold behavior of nanosheet transistors

A novel ballistic model for the subthreshold current of nanosheet transistors is successfully developed based on the Landauer approach with the three-dimensional number of channels. The ballistic threshold voltage can also be achieved through the calculated free charge density induced by the three-dimensional density-of-states equal to the substrate doping concentration. It indicates that under the low drain voltage corresponding to the Fermi distribution function, the subthreshold current is mainly governed by the low contact potential. However, under the high drain voltage corresponding to the Fermi distribution function, the thermal voltage, instead of the contact potential between the source and drain, initiates the subthreshold current. Besides subthreshold current and threshold voltage, the ballistic conductance and subthreshold swing are also revealed in the subthreshold conduction. It indicates that the thin silicon, thin gate oxide, heavy substrate doping density, and high work function will alleviate the ballistic effects, decrease the subthreshold current/swing, and increase the threshold voltage/ballistic resistance.

Novel hybrid-CMOS inverter utilizing phase transition material for enhancing digital logic performance at lower operating voltages

This research paper introduces a novel design for a hybrid-CMOS inverter using vanadium dioxide (VO2), a phase transition material. The proposed inverter exhibits a remarkably steep transition for falling logic at the output(1–0). By leveraging the insulating to metallic current density (IC-IMT) of VO2, the depth and gain of this transition can be finely tuned. Notably, a higher IC-IMT value yields a greater gain in the transition slope. In comparison to a traditional CMOS inverter, the designed inverter demonstrates several advantages. It achieves higher values of lower noise margin (NML) and significantly reduces static power dissipation by 97.7%. These promising outcomes present an exciting opportunity for designing inverters at lower drain voltages, especially in devices operating at lower technology nodes. Furthermore, the hybrid-CMOS inverter is designed to excel in the sub-threshold region of operation, resulting in elevated values of lower noise margin and reduced leakage current values.

A ballistic model for subthreshold current and threshold voltage of the dual-material-gate nanosheet MOSFET

— A ballistic model for subthreshold current of the dual-material-gate (DMG) nanosheet (NS) MOSFET is developed based on the Landauer approach, three-dimensional scaling equation, and the continuity of subthreshold current at the interface between the control gate and screen gate in the channel, The work function difference between the screen gate and control gate can be converted into the new interface-quasi-fermi-potential (IQFP) at the junction between different gate regions. Through the IQFP, the ballistic subthreshold current for DMG NS MOSFET is successfully developed. With the determined subthreshold current, the ballistic threshold voltage can also be achieved by the constant current method. Under the low and high drain voltage corresponding to their IQFPs, the subthreshold behavior is mainly governed by the contact potential and thermal voltage, respectively. Furthermore, Ohm's law regarding ballistic resistance for the DMG NS MOSFET can still be valid in the subthreshold conduction.

The defects of reported TID reinforced structures and the improved structure

We find that the previously reported P-edge N-Metal-Oxide-Semiconductor Field-Effect Transistor (NMOSFET) and dummy gate-assisted (DGA) NMOSFET, to resist the total ionizing dose (TID) effect, have a fatal drawback in that they can only work under a very low drain voltage (Vdd). This paper proposes and demonstrates an improved structure, called P+ edge source NMOS (PES-NMOS), in which the heavily P+ doped belts are only formed on both sides of the source region close to the shallow trench isolation (STI). Both the TCAD software simulations and radiation experiments show that the turn-off current (Ioff) of the PES-NMOS device under 1.8 V Vdd is about 4 to 5 orders of magnitude smaller than that of the control group without reinforcement structure at 300 krad(Si) TID. This result proves that the PES-NMOS can well resist the TID effect and solve the fatal drawback of the reported structures. With the continuous progress of the CMOS process, the thickness of gate oxide becomes very thin, while STI is relatively thick, so the total dose effect on STI is still significant. Therefore, the importance of using the PES-NMOS to suppress the parasitic channel of STI and overcome the shortcomings of the ELT is increasing. Index termsP+ edge source NMOS, total ionizing dose(TID) effect, radiation experiments, radiation hardening by design(RHBD).

General Model for Charge Carriers Transport in Electrolyte‐Gated Transistors

AbstractA charge carrier transport model able to describe the typical modes of operation and some non‐ideal ones from electrolyte‐gated field effect transistors and organic electrochemical transistors (OECTs) is proposed. The analysis include the effect of 2D or 3D percolation transport (PT) and the influence of a shallow exponential trap distribution on the transport. Under these considerations, a non‐constant accumulation layer thickness along the channel can be formed, resulting in a non‐constant effective mobility. The accumulation thickness can depict 2D or 3D PT or even a transition between them. This transition can produce a non‐ideal profile between the linear and saturation regimes in the output curve, region in which a lump appears. Other analyzed phenomenon is the non‐linear behavior for low drain voltage in the output curve, even considering an ohmic contact. This phenomenon is attributed to the traps distribution profile into the semiconductor and the thin accumulation layer thickness close to the injection contact. The conditions when the linear field effect mobility is higher or lower than the saturation one is also analyzed. Finally, electrolyte‐gated organic field effect transistors and OECT experimental data are successfully fitted with this model showing its versatility.

High-performance asymmetric electrode structured light-stimulated synaptic transistor for artificial neural networks.

Photonics neuromorphic computing shows great prospects due to the advantages of low latency, low power consumption and high bandwidth. Transistors with asymmetric electrode structures are receiving increasing attention due to their low power consumption, high optical response, and simple preparation technology. However, intelligent optical synapses constructed by asymmetric electrodes are still lacking systematic research and mechanism analysis. Herein, we present an asymmetric electrode structure of the light-stimulated synaptic transistor (As-LSST) with a bulk heterojunction as the semiconductor layer. The As-LSST exhibits superior electrical properties, photosensitivity and multiple biological synaptic functions, including excitatory postsynaptic currents, paired-pulse facilitation, and long-term memory. Benefitting from the asymmetric electrode configuration, the devices can operate under a very low drain voltage of 1 × 10-7 V, and achieve an ultra-low energy consumption of 2.14 × 10-18 J per light stimulus event. Subsequently, As-LSST implemented the optical logic function and associative learning. Utilizing As-LSST, an artificial neural network (ANN) with ultra-high recognition rate (over 97.5%) of handwritten numbers was constructed. This work presents an easily-accessible concept for future neuromorphic computing and intelligent electronic devices.

A Capacitance Model for Front- and Back-Gate Threshold Voltage Computation of Ultra-Thin-Body and BOX Double-Insulating Silicon-on-Diamond MOSFET

In this paper, a capacitance model for near threshold voltage computation of Ultra-Thin-Body and BOX (UTBB) Double-Insulating (DI) Silicon-on-Diamond (SOD) MOSFET is proposed. The transistor has a second insulating layer on top of the first insulating layer of a conventional SOD MOSFET which partially covers the diamond layer. The device’s simulation results of the front- and back-gate threshold voltages and the computed model’s threshold voltages - in terms of gate oxide thickness, silicon film layer thickness, first and second insulating layer thicknesses - are compared. In addition, length of the source/drain overlap with the second insulating layer is varied and the device simulation results are compared with those of the model findings. Results of the aforesaid comparison are found to be promising; more than 20 mV change in front-gate threshold voltage is observed at the range of 5 nm to 43 nm. Moreover, the model is found to be applicable in computations of front- and back-gate threshold voltage of 22 nm DI UTBB SOD MOSFET for low drain voltages. Finally, the model’s physical findings present insight on the device’s parameters that directly influence the threshold voltage

Perovskite/InGaZnO-Based Reconfigurable Optoelectronic Device

Herein, we demonstrate a drain voltage modulated reconfigurable optoelectronic device. It can switch work modes in unipolar response and bipolar response for photodetection mode and neuromorphic photo preprocessing, respectively. The device is fabricated based on perovskite-decorated photogate structure with an indium gallium zinc oxide (IGZO) channel, in which the channel photo-generated carrier concentration can be tuned by applied drain voltage. Under low drain voltage, the photodetection mode is achieved, exhibiting a high responsivity up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4\times 10$ </tex-math></inline-formula> 2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{A}\cdot \text{W}$ </tex-math></inline-formula> −1. While under high drain voltage, a bipolar response behavior is achieved, in which the low-intensity light induces a negative photo response (NPR) and the high-intensity light leads to a positive photo response (PPR). Furthermore, after contrast-enhanced preprocessing of bipolar devices, the recognition accuracy is enhanced from 89.4% to 92.8% and the efficiency is also improved. This work may contribute to the development of reconfigurable optoelectronic devices and neuromorphic photo preprocessing.

The Impact of a Paraelectric layer in the FE/DE Stack on Performance of NCFET

In this paper, through TCAD simulations, we show that the introduction of a thin paraelectric (PE) layer between the ferroelectric (FE) and dielectric (DE) layers in an MFIS structure, expands the design space for the FE layer enabling hysteresis-free and steep subthreshold behavior, even with a thicker FE layer. This can be explained by analyzing the FE-PE stack from a capacitance perspective where the thickness of the PE layer in the FE-PE stack has the effect of reducing the FE layer thickness, while also reducing the remnant polarization. Finally, for the same FE-PE-DE stack, analog performance parameters such as \(\frac {G_{m}}{G_{ds}}\) and \(\frac {G_{m}}{I_{d}}\) are analyzed, showing good characteristics over a wide range of gate lengths, at low drain voltages, thus demonstrating applicability for low power applications.

(Invited, Digital Presentation) Oxide TFTs Based on Semiconductors and Semimetals

A bottleneck issue of oxide TFTs is the instability under bias stresses and illuminations. Furthermore, the carrier mobility needs improvement for high pixel density and high brightness displays. Here, we use a high work-function Schottky source contact to enable depletion around the TFT source region. This results in a high intrinsic immunity to negative bias illumination stress, no obvious short channel effect, and extremely flat current saturation at low drain voltages. A voltage gain reaching 23,000 V/V is obtained due to the flat saturation current, which is the highest ever achieved with a solid-state transistor. Furthermore, the Schottky barrier depletion allows to utilize ITO to replace IGZO as the channel layer, which significantly enhances carrier mobility. Because ITO is used for both channel and drain electrode, the TFT appears to have no channel, enabling aggressive scaling for a significant increase in flat-panel display pixel aperture ratio, brightness and pixel density.

High transconductance and current density in field effect transistors using arrays of bundled semiconducting carbon nanotubes

We examine if the bundling of semiconducting carbon nanotubes (CNTs) can increase the transconductance and on-state current density of field effect transistors (FETs) made from arrays of aligned, polymer-wrapped CNTs. Arrays with packing density ranging from 20 to 50 bundles μm−1 are created via tangential flow interfacial self-assembly, and the transconductance and saturated on-state current density of FETs with either (i) strong ionic gel gates or (ii) weak 15 nm SiO2 back gates are measured vs the degree of bundling. Both transconductance and on-state current significantly increase as median bundle height increases from 2 to 4 nm, but only when the strongly coupled ionic gel gate is used. Such devices tested at −0.6 V drain voltage achieve transconductance as high as 50 μS per bundle and 2 mS μm−1 and on-state current as high as 1.7 mA μm−1. At low drain voltages, the off-current also increases with bundling, but on/off ratios of ∼105 are still possible if the largest (95th percentile) bundles in an array are limited to ∼5 nm in size. Radio frequency devices with strong, wraparound dielectric gates may benefit from increased device performance by using moderately bundled as opposed to individualized CNTs in arrays.

FUNDAMENTAL LIMITS FOR THE LENGTH OF CONDUCTION CHANNEL IN THE FET ON TRANSITION METALS DICHALCOGENIDE SINGLE LAYER BASE

The modeling of the limits of functionality for the FET with conduction channel on transition metals dichalcogenide single layer base and with different source/drain contacts material was performed in this article. The quantum mechanical transparency of the channel barrier was calculated with allowance for the realistic form of the barrier potential. It is demonstrated, that the FET with 4-nm channel of n-MoS2 and MoS2 (metallic modification) source/drain contacts retains high level of functionality for the range of comparatively low gate and drain voltages (the barrier transparency is lower than ½). The similar FET with Pt source/drain contacts, when Schottky barrier is essentially higher and the barrier transparency is essentially lower, keep it’s functionality for the 2 nm channel as well for all the realistic values of gate and drain voltages. The similar result was obtained for the FET with p-WSe2 channel and Pd contacts as well. The obtained estimations confirm the possibility of the complementary inverter on MoS2 n-type FET and WSe2 p-type FET with ultra-short channels in 2–4 nm range.

Arrays of Bundled Semiconducting Carbon Nanotubes for High Transconductance Field Effect Transistors

Forming aligned arrays from bundled (rather than individualized) semiconducting carbon nanotubes can beneficially increase the density of nanotubes in the channel of field effect transistors (FETs). Here, we prepare aligned arrays of bundles at a density of 20 – 50 bundles μm-1 via tangential flow interfacial self-assembly and show that bundles can increase the transconductance of FETs when a strong gate is used. When encapsulated with an ion gel gate, the transconductance and saturated on-current increases as the diameter of the bundles increases. Devices tested at -0.6 V drain voltage using an ion gel gate achieve transconductance as high as 50 μS per bundle and 2000 μS μm-1 and on-state current as high as 1.7 mA μm-1. At low drain voltages the off-current also increases with bundling, but on/off ratios of ~105 are possible if the bundle size is limited to ~ 5 nm. Radio frequency devices with very strong gates may benefit from the increased device performance by using moderately bundled semiconducting carbon nanotube arrays.Figure Caption: Panel (a) has transfer curves from 4 devices each with ~42 CNTs-bundles μm-1 but with different median bundle heights. Devices with larger bundles have higher transconductance and saturated on-currents. Panel (b) shows the transconductance per bundle vs the median bundle height and shows the positive correlation between bundle size (height) and transconductance per bundle. Panel (c) is a rendering of a large bundle formed from polymer wrapped CNTs. Figure 1

Power Compression and Phase Analysis of GaN HEMT for Microwave Receiver Protection

This paper reports a high-performance microwave receiver protector (RP) based on a single gallium nitride (GaN) high electron mobility transistor (HEMT) at an operation frequency of 30 to 3000 MHz. The HEMT-based RP exhibits multi features: high power compression, constant output power, tunable threshold power level, and insensitivity to frequency variation. With a low drain voltage (Vds) of 3 V, constant output power of 9.9 dBm was acquired for input power over its threshold power of 3.2 dBm. Power compression of 13.3 dB was achieved at the input power of Pin = 20 dBm. In addition, adjustable threshold power level Pth could be obtained by merely tuning drain voltage. Transducer gain measurement results were employed to explain the occurrence of output power saturation. Relatively higher Pth was linked to wider gate voltage swing which extended the linear region of the Pout-Pin characteristic. In addition, the GaN HEMT’s power compression capability shows great immunity to frequency variation, which is promising for protecting sensitive receiver components at both low and high frequencies. Finally, the phase shift of the GaN HEMT RP at high input power was measured and analyzed by the nonlinear behaviors of input capacitance Cgs.

Device operation and physical mechanism of asymmetric junctionless tunnel field-effect transistors designed to suppress coupled short-channel/short-drain effects and promote on-current switching for ultralow-voltage CMOS applications

Scaled tunnel field-effect transistors (TFETs) endure severe short-channel and short-drain effects caused by direct source-to-drain and body-to-drain tunneling. This study numerically examined a Si-based asymmetric junctionless TFET (AJ-TFET) architecture for suppressing coupled short-channel and short-drain effects in and improving the on-current switching of TFET devices for ultralow-voltage CMOS applications. The junctional drain/body facilitates the extending of the off-state tunnel barrier into the drain, enhancing robustness against short-channel and short-drain effects. The junctionless source/body can minimize lateral coupling and thus lead to efficient switching in a TFET, thus generating steep on–off switching swings. The results revealed that in contrast to conventional PIN-TFETs, the AJ-TFET evaluated in this study exhibited considerably lower swing levels and higher current levels. The voltage-scaled AJ-TFET retained excellent subthreshold behaviors and short-channel robustness, offering adequate on-current levels along with minimized leakage levels. Incorporating high-k gate dielectrics into the devices enabled extra on-current boosting and swing minimization, further extending the deep-swing, high-current operation region. Because of their excellent on–off switching and on-current enhancement, the extremely scaled AJ-TFET could operate adequately at low gate and drain voltages (0.3–0.5 V); therefore, they are promising candidates for use in ultralow-voltage energy-efficient applications.

The Root Cause Behind a Peculiar Dual-Mode ON-State Breakdown in High Voltage LDMOS

This work investigates the often-observed current discontinuity much before avalanche breakdown (dual-mode ON-state breakdown) in the output characteristics of a laterally diffused metal–oxide–semiconductor (LDMOS) device. The physical origin of the dual-mode ON-state breakdown, often reasoned to be due to parasitic n-p-n, is shown to be independent of parasitic n-p-n. A laterally diffused tunnel FET (LDTFET) with a drift region profile same as LDMOS was experimented to rule out the effect of parasitic n-p-n. LDTFET device, which intrinsically cannot have parasitic n-p-n, also shows similar output characteristics with dual-mode ON-state breakdown. This proved that the parasitic bipolar turn-on is not the root cause behind the observed behavior. On the contrary, it was found to be dependent on the onset of space charge modulation (SCM) in the drift region, resulting in localized high electric field and quasi-saturation effects at low drain voltages. The effect of mobility degradation due to the high electric field in the drift region post-SCM is also presented, emphasizing that the observed behavior results from the high field mobility degradation of majority charge carriers.

High-efficiency Class-F Power Amplifier with a New Design of Input Matching Network

This paper presents a novel access to develop a class-F power amplifier with high power-added efficiency (PAE). The main goal of the proposed PA is to obtain high PAE. The proposed HCC consists a design of output matching circuit (OMN) and input matching combined with a symmetric low-pass filter (LPF) reported. To accomplish a high-efficiency performance, a low-voltage pHEMT in the circuit was executed to supply the required dc-supply voltage. It yielded nth harmonic suppression and high-power added efficiency (PAE). The simulation was carried out using harmonic balance analysis. The power amplifier proposed in this study was fabricated at fundamental frequency of 1 GHz with PAE of 80% and DE of 86% under 12.3dBm input power and very low drain voltage of 2 V. This class-F PA manufactured with such features can be utilized for power amplification in wireless transmitter communication systems.

Ultralow‐Power Synaptic Transistors Based on Ta2O5/Al2O3 Bilayer Dielectric for Algebraic Arithmetic

AbstractMultifarious artificial synaptic devices are extensively proposed in the field of neuromorphic hardware systems for their applicability in promising parallel computer architecture, which is preferred to classical Von Neumann architecture in numerous and complex information processing. Besides the ability to mimic typical biological synaptic behaviors, low power consumption is critical for the synaptic devices in the neuromorphic hardware system.In this paper, ultralow‐power Ta2O5/Al2O3 bilayer‐gate‐dielectric synaptic transistors (TABSTs) with low‐temperature atomic layer deposited dielectric are proposed. The TABSTs show power consumption as low as 19.9 aJ per synaptic event successfully at a low drain voltage of 0.001 V and a short pulse width of 1 ms. Essential synaptic behaviors including excitatory postsynaptic current, inhibitory postsynaptic current, spike‐amplitude‐dependent plasticity, spike‐duration‐dependent plasticity, paired pulse facilitation, long‐term potentiation, long‐term depression, the transition from short‐term memory to long‐term memory as well as learning and forgetting abilities are well mimicked by the TABSTs. Moreover, algebraic arithmetic operations such as addition, subtraction, multiplication, and division are also implemented by the TABSTs. This work provides a promising approach to emerging neuromorphic systems.