Novel hybrid-CMOS inverter utilizing phase transition material for enhancing digital logic performance at lower operating voltages

Abstract

This research paper introduces a novel design for a hybrid-CMOS inverter using vanadium dioxide (VO2), a phase transition material. The proposed inverter exhibits a remarkably steep transition for falling logic at the output(1–0). By leveraging the insulating to metallic current density (IC-IMT) of VO2, the depth and gain of this transition can be finely tuned. Notably, a higher IC-IMT value yields a greater gain in the transition slope. In comparison to a traditional CMOS inverter, the designed inverter demonstrates several advantages. It achieves higher values of lower noise margin (NML) and significantly reduces static power dissipation by 97.7%. These promising outcomes present an exciting opportunity for designing inverters at lower drain voltages, especially in devices operating at lower technology nodes. Furthermore, the hybrid-CMOS inverter is designed to excel in the sub-threshold region of operation, resulting in elevated values of lower noise margin and reduced leakage current values.