Lightly Doped Drain Structures Research Articles

Fabrication and characterization of T-gate polysilicon thin-film transistors with lightly-doped drain

We report detailed fabrication and characterization of poly-Si thin-film transistors (TFTs) with T-shaped gate (T-gate) and lightly-doped drain (LDD) structures. The formation of the LDD underneath the wings of a T-gate primarily relies on the shadowing of implanted dopants during the implantation of source and drain. Therefore, the fabrication of LDD structures in our proposed T-gate poly-Si TFTs can save a number of process steps as compared to conventional poly-Si TFTs with LDD structures. Our fabricated T-gated poly-Si TFTs with LDD structures not only exhibit suppressed off-state leakage current but also show a significant improvement in on-state current as compared to that of conventional poly-Si TFTs with the same top-gate dimension.

6.4: The Effect of LDD Structure on the Characteristics of TFT Devices

Low temperature polycrystalline silicon thin film transistor (LTPS TFT) has a wide application prospect in flat panel display and other fields due to its higher carrier mobility and better conductivity. Motivated with the development of flat‐panel display devices targeting higher resolution, it is imperative to carry out research in small‐sized LTPS TFT technology. When the channel size is decreased to a certain extent, the effect of the gradual channel approximation is no longer valid. As a result, the short channel effect and the hot carrier effect will have significant impacts on the LTPS TFT devices. To alleviate and eventually to eliminate these two effects, we introduce and implement the Lightly Doped Drain (LDD) structure in the LTPS TFT device. LDD is a technology by adding lightly doped region between source and drain in a TFT, its series resistance is increased, thereby greatly reducing the electric field of drain, resulting in much less hot carrier effect and short channel effect. However, the introduction of LDD structure might have some adverse impacts on the characteristics of LTPS TFT if not optimized. In this paper, we studied the influence of different LDD structures on TFT performance, finding out the optimal LDD structure.

Anomalous capacitance characteristics of TFTs with LDD structures in the saturation region

The effect of lightly doped drain (LDD) doping concentration on the capacitance of a low-temperature polycrystalline silicon (LTPS) thin-film transistor (TFT) is investigated. An anomalous gate-to-source capacitance phenomenon is observed: first, the capacitance decreases, and then it increases according to the gate voltage in the saturation region. This phenomenon is not affected by the subgap density-of-states and arises as the doping concentration of the LDD region is reduced. To investigate the effects of each source and the drain LDD dose on the gate-to-source capacitance, two-dimensional device simulations were conducted in which each dose of the source and drain LDD was changed individually. The reduced controllability of the source voltage to the gate charge in the saturation region due to the increased resistance of the source LDD region with low LDD dose is identified as the reason for this anomalous capacitance phenomenon.

A threshold voltage analytical model for high-k gate dielectric MOSFETs with fully overlapped lightly doped drain structures

We investigate the influence of voltage drop across the lightly doped drain (LDD) region and the built-in potential on MOSFETs, and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overlapped LDD structures by solving the two-dimensional Poisson's equation in the silicon and gate dielectric layers. The model can predict the fringing-induced barrier lowering effect and the short channel effect. It is also valid for non-LDD MOSFETs. Based on this model, the relationship between threshold voltage roll-off and three parameters, channel length, drain voltage and gate dielectric permittivity, is investigated. Compared with the non-LDD MOSFET, the LDD MOSFET depends slightly on channel length, drain voltage, and gate dielectric permittivity. The model is verified at the end of the paper.

Analysis of Hot Carrier Effect in Low-Temperature Poly-Si Gate-Overlapped Lightly Doped Drain Thin Film Transistors

Low-temperature poly-Si thin film transistor (TFT) is widely expected as the most promising technology for realizing system on panels. We fabricated the poly-Si TFT with a gate-overlapped Lightly Doped Drain (GOLD) structure. Reliability was evaluated using electrical stress comparing conventional lightly doped drain (LDD) and single drain structures. We have confirmed that the degradation of ON current and the field effect mobility was very small compared to the case of conventional LDD or non-LDD structures. We have analyzed the reliability of the GOLD TFT using a two-dimensional device simulator and emission microscope. We found that more hot electrons are generated in GOLD TFT, however, a vertical negative field plays a dominant role for improving the reliability of the GOLD TFT. Based on the experimental and theoretical results, we proposed a new reliability model. Impact ionization occurs far from the interface between the oxide and polysilicon by the vertical negative field. Therefore, the damaged region in poly-Si does not affect such electrical performance as drain current.

A new self-consistent model for the analysis of hot-carrier induced degradation in lightly doped drain (LDD) and gate overlapped LDD polysilicon TFTs

Hot-carrier induced degradation is a main issue in the electrical stability of polysilicon TFTs and drain field relief architectures have been introduced, such as lightly doped drain (LDD) and gate overlapped LDD (GOLDD), to improve the stability. Bias-stress experiments were performed on both LDD and GOLDD structures, biasing the devices above pinch-off at constant V g and different V ds. While the LDD structure presented considerable hot-carrier induced degradation, GOLDD devices were characterised by a very high electrical stability. To explain such a difference in electrical stability, we first analysed the spatial distributions of the electric fields, which are lower in GOLDD structures. In addition, we developed a new model to describe the hot-carrier induced degradation, based on the correlation between hot carrier injection currents and interface state generation. Indeed, hot carrier injection is known to produce interface states and oxide trapped charge, and, depending upon their spatial distribution, can strongly influence the local electric fields as well as the current. The proposed model nicely reproduces the degraded characteristics, thus providing indications on the spatial distribution of the generated interface states.

핫 캐리어 신뢰성 개선을 위한 새로운 LDD 구조에 대한 연구

The hot carried degradation in a metal oxide semiconductor device has been one of the most serious concerns for MOS-ULSI. In this paper, three types of LDD(lightly doped drain) structure for suppression of hot carried degradation, such as decreasing of performance due to spacer-induced degradation and increase of series resistance will be investigated. in this study, LDD-nMOSFETs used had three different drain structure, (1) conventional surface type LDD(SL), (2) Buried type LDD(BL), (3) Surface implantation type LDD(SI). As experimental results, the surface implantation the LDD structure showed that improved hot carrier lifetime to comparison with conventional surface and buried type LDD structures.

Enhanced hot-carrier-degradation in LDD MOSFET's under pulsed stress

Hot-carrier degradation of lightly doped drain (LDD) MOSFET's under ac stress is investigated. Enhanced ac degradation occurs in LDD MOSFET's as well as in single-drain MOSFET's. However, there is a peculiar degradation mechanism in LDD MOSFET's. For single-drain MOSFET's, enhanced ac degradation appears in both threshold voltage and transconductance at stress drain voltages larger than a critical value. On the other hand, for LDD MOSFET's, although the enhanced degradation in threshold voltage and transconductance appears at stress drain voltages larger than a critical value, the enhanced degradation in transconductance appears even under stress drain voltages lower than the critical value. The difference in the ac-enhanced degradation between LDD and single-drain structures can be explained by a hot hole generated neutral-electron-trap model and the change in hot-hole-injected oxide region according to stress bias conditions. >

Anomalous hot-carrier behavior for LDD p-channel transistors

It has previously been reported that gradual junction p-channel transistors can have shorter lifetimes under hot-carrier stress conditions than abrupt junction devices (see IEEE Trans. Electron Devices, vol. 39, p. 2290-98, 1992). Here, the work is extended to LDD (lightly doped drain) structures. p-MOS hot-carrier effects are examined for deep submicron structures with abrupt and LDD junctions. It is shown that, contrary to the case of n-MOS transistors, the lifetimes for hot-carrier stress of the LDD p-MOS transistors are actually shorter than their abrupt junction counterparts, in the range of LDD dopings examined here. This is explained in terms of two competing mechanisms, gate electronic injection, which decreases for the LDD junctions, and the size of the damage region in the oxide, which increases for the LDD junctions. It is concluded that using LDD-type structures for hot-carrier control does not automatically guarantee longer lifetimes. >

Hot-carrier effects in scaled MOS devices

A universal guideline and state-of-the-art hot-carrier effects in scaled MOSFETs are reviewed and discussed from the viewpoints of 1) DC and AC hot-carrier effects, 2) hot-carrier detrapping phenomena, 3) mechanical stress effects on hot-carrier phenomena, and 4) hot-carrier resistant device structures. In the deep-submicron region, the hot-carrier applicable voltage is less than 3 V, so AC hot-carrier effects from the dynamic operation of actual circuits should be taken into account. Despite much experimentation and analysis, there is still no universally accepted theory that explain the AC degradation mechanism. This is because the noise caused by the wiring inductance in ULSI circuits and in measurement systems screens the intrinsic AC hot-carrier effects. Here, AC hot-carrier degradation enhanced by gate pulse-induced-noise is analyzed experimentally and theoretically. After eliminating the noise problem, it is found that AC hot-carrier degradation in LDD (Lightly doped drain) and GOLD (gate-drain overlapped device) structures can be estimated based on DC degradation in terms of the effective stress time which takes the duty ratio into account. In addition, it is found that the noise is negligible when the wiring inductance is smaller that 80 nH (250 mω), which is important for future circuit design. Furthermore, hot-carrier detrapping effects, especially in p-channel MOS devices, and hot-carrier phenomena under mechanical stress are investigated experimentally to better understand the underlying hot-carrier physics. Finally, future hot-carrier resistant device structures are discussed.

An experimental study on the short-channel effects in undergated polysilicon thin-film transistors with and without lightly doped drain structures

Short-channel effects are studied for undergated polysilicon thin-film transistors (TFTs). Although a simple lightly doped drain (LDD) structure can minimize the effects, a much longer LDD region is required than in a bulk transistor. In addition to significant effects similar to bulk transistors, the leakage current is more affected by variations of the channel length and drain bias than it is in a bulk transistor due to the granular structures of the polysilicon films and the enhanced junction field in the fully depleted structure. As results, variations of the ON current, OFF current, and their ratio are dramatic without the LDD structure. >

An evaluation of conventional and LDD devices for submicron geometries

As transistor dimensions shrink, lightly-doped drain (LDD) device structures are expected to improve MOSFET reliability at the expense of current drive due to parasitic source/drain resistance. In this study, both conventional and two types of LDD processes are evaluated in terms of parametric data and hot carrier degradation. n-Channel LDD devices are shown to reduce short-channel effects associated with scaling of gate lengths. The effect of reduced current drive of the LDD structure on circuit speed is shown to be partially compensated by the reduced overlap capacitance. The hot carrier reliability of both device structures was compared by plotting device lifetimes for several parameters vs substrate current. It was shown that LDD devices will reduce hot carrier effects not only by lowering the peak electric field (and therefore I b) but also by minimizing the influence of carriers injected into the gate oxide. This is presumed to be the result of the different spatial distribution of charge injection for LDD structures compared to conventional transistors. Optimized LDD devices can be expected to achieve one to three orders of magnitude lifetime increase when compared to conventional n-channel MOS transistors with equal current drive.

An analytical model for the lateral channel electric field in LDD structures

An analytical model for the lateral channel electric field in lightly doped drain (LDD) MOSFETs is developed from a pseudo-two-dimensional analysis. The model gives a prediction of the channel field when the lightly doped region is both fully depleted and partially depleted. The normal field mobility degradation and variation of the saturation field E/sub sat/ with gate voltage have been taken into account in the model. The boundary conditions for determining the pinch-off point L/sub sat/ proposed in the model along with the normal field mobility degradation consideration make possible the prediction of the variation of the pinch-off with the gate bias and the maximum value of the electric field E/sub max/. The differences between this model, existing models, and two-dimensional numerical simulations are discussed. >

Application of electrical effective channel length and external resistance measurement techniques to a submicrometer CMOS process

The practical applications and limitations of four methods for extracting the effective channel length (L/sub eff/) and series resistance (R/sub ext/) parameters for MOS devices are studied. The methods are: GD (gate drive) using fixed-current V/sub t/ or GD(I/sub ds/); SBGD (substrate-bias GD) using fixed-current V/sub t/ or SBGD (I/sub ds/); GD using maximum slope V/sub t/ or GD (G/sub m/); and SBGD using maximum slope V/sub t/ or SBGD (G/sub m/). Conventional and two LDD (lightly doped drain) structures fabricated in a submicrometer CMOS process are used. The results indicate that all the extraction methods are applicable to both n-channel and p-channel devices, although some are only valid over a small range of gate biases. Inconsistencies in applying V/sub t/ calculations to the extraction equations set a lower limit for V/sub gst/ of approximately 0.5 V, while the upper limit of 2.0-4.0 V arises due to imprecision in R/sub ds/ measurements influencing the double regression steps involved in the techniques. The SBGD (I/sub ds/) method was applicable over a wider range of bias conditions than the other techniques analyzed and is easier to implement.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An advanced single-level polysilicon submicrometer BiCMOS technology

An advanced VLSI (very large scale integration) technology providing high-performance n-p-n bipolar (f/sub T/=9 GHz) and submicrometer gate-length MOS (metal-oxide-semiconductor) transistors is described. This technology is intended for high-speed logic circuits operating at 5 V, where a high level of circuit integration and low power consumption is required. Features include vertical n-p-n transistors with walled, self-aligned polysilicon emitters and lightly doped extrinsic base (LDEB) extensions MOS transistors feature complementary-doped polysilicon gates and LDD (lightly doped drain) structures for both NMOS and PMOS. Optional buried contacts between the polysilicon layer and all junctions in the silicon substrate are provided. Polysilicon emitters, MOS gates, base/collector, and source/drain regions are silicided. In addition, a fully planarized metal interconnect scheme incorporating nonselective CVD (chemical-vapor-deposited) tungsten and vertical-walled contacts and vias is utilized. >

46th Annual Device Research Conference

The history and tremendous progress in MOS integrated circuit technology has been dominated by the scaling of device feature size and the increased level of integration. Feature size and integration level have progressed from around 25 pm and 10-100 transistors on a single chip in the mid 1960’s to 0.8 pm and over 4 million transistors in today’s products. The simple conventional MOS transistor was used quite successfully in the successive generations of technologies until the early 1980’s. In the late 1970’s and early 1980’s the continuously decreasing feature size (transistor gate length) combined with limited (step function) decreases in the power supply voltage resulted in sufficiently high electric fields to cause adverse “hot camer” effects. These hot camers degrade MOS transistor performance by increasing interface state density (thus reducing transconductance), and by becoming trapped in the gate dielectric (thus shifting threshold voltage). As a result, a new engineering activity called “drain engineering” arose, and in the early 1980’s, a major change was made in the source/drain structure of the transistor which is most generically known as the LDD (lightly doped drain) transistor today. There are numerous types of LDD structures, but all forms are based on the concept of inserting an intermediate drain doping between the MOS channel and the heavily doped drain region. This serves the purpose to “grade” the drain and drop the drain voltage over a greater distance, thus reducing the high electric fields. As the technology has advanced below 1 pm feature size and

Buried and graded/buried LDD structures for improved hot-electron reliability

New and graded/buried lightly doped drain (LDD) structures have been demonstrated, for the first time, to improve significantly the hot-electron reliability of NMOS devices. Both LDD structures have peak doping of the n- spacer implant approximately 1000 A below the Si-SiO 2 interface forming a buried n- spacer near the drain region. In the graded/buried LDD structure the junction of the buried n- spacer is further graded by an additional low-dose phosphorus spacer implant.

An analytical one-dimensional model for lightly doped drain (LDD) MOSFET devices

An analytic one-dimensional model for lightly doped drain (LDD) MOSFET devices is presented. This model decomposes the LDD device into an intrinsic MOSFET in series with n-source and drain diffusion. A conventional charge control model with a pseudo two-dimensional approach was used to calculate the current flow in the intrinsic MOSFET. The voltage drops in the n-source and drain, including both IR drops and voltage drop across the depletion region of the drain were calculated analytically. By reconstructing all the voltage drops across contact, source/drain, and channel regions, the calculated drain currents as a function of terminal voltages agree well with experimental data. Device optimization is also presented by using this analytical model for full LDD and As-P double diffused LDD structures.