Hot-carrier effects in scaled MOS devices

Abstract

A universal guideline and state-of-the-art hot-carrier effects in scaled MOSFETs are reviewed and discussed from the viewpoints of 1) DC and AC hot-carrier effects, 2) hot-carrier detrapping phenomena, 3) mechanical stress effects on hot-carrier phenomena, and 4) hot-carrier resistant device structures. In the deep-submicron region, the hot-carrier applicable voltage is less than 3 V, so AC hot-carrier effects from the dynamic operation of actual circuits should be taken into account. Despite much experimentation and analysis, there is still no universally accepted theory that explain the AC degradation mechanism. This is because the noise caused by the wiring inductance in ULSI circuits and in measurement systems screens the intrinsic AC hot-carrier effects. Here, AC hot-carrier degradation enhanced by gate pulse-induced-noise is analyzed experimentally and theoretically. After eliminating the noise problem, it is found that AC hot-carrier degradation in LDD (Lightly doped drain) and GOLD (gate-drain overlapped device) structures can be estimated based on DC degradation in terms of the effective stress time which takes the duty ratio into account. In addition, it is found that the noise is negligible when the wiring inductance is smaller that 80 nH (250 mω), which is important for future circuit design. Furthermore, hot-carrier detrapping effects, especially in p-channel MOS devices, and hot-carrier phenomena under mechanical stress are investigated experimentally to better understand the underlying hot-carrier physics. Finally, future hot-carrier resistant device structures are discussed.