An evaluation of conventional and LDD devices for submicron geometries

Abstract

As transistor dimensions shrink, lightly-doped drain (LDD) device structures are expected to improve MOSFET reliability at the expense of current drive due to parasitic source/drain resistance. In this study, both conventional and two types of LDD processes are evaluated in terms of parametric data and hot carrier degradation. n-Channel LDD devices are shown to reduce short-channel effects associated with scaling of gate lengths. The effect of reduced current drive of the LDD structure on circuit speed is shown to be partially compensated by the reduced overlap capacitance. The hot carrier reliability of both device structures was compared by plotting device lifetimes for several parameters vs substrate current. It was shown that LDD devices will reduce hot carrier effects not only by lowering the peak electric field (and therefore I b) but also by minimizing the influence of carriers injected into the gate oxide. This is presumed to be the result of the different spatial distribution of charge injection for LDD structures compared to conventional transistors. Optimized LDD devices can be expected to achieve one to three orders of magnitude lifetime increase when compared to conventional n-channel MOS transistors with equal current drive.