Two-dimensional drain engineering for leakage reduction in thin-film transistors

Abstract

The variation of drain dopant profiles in two dimensions is shown to be superior to tradi- tional drain-engineering techniques for achieving low leakage in poly-Si thin-film transistors. Polycrystalline silicon (poly-Si) thin-film transistors (TFTs) are used in applications such as active- matrix liquid-crystal displays and image sensors, which have stringent TFT-leakage requirements. Experimental studies have shown that one of the main factors which affects leakage current is the electric-field strength in the channel region near the drain'. Lightly doped drain (LDD) structures have previously been used to reduce the electric field at the drain junction and thereby reduce TFT leakage current2. In these structures, the LDD region is placed between the channel and the heavily doped drain and spans the entire thickness of the channel, so that the drain dopant concentration varies only in one dimension (parallel to the gate). LDD structures are difficult to implement in poly-Si due to the poor controllability of dopant activation at concentrations below -lo1* ~m-~: underdoping of the LDD region results in decreased drive current in offset-drain structures, while over-doping results in a loss of the benefit of reduced leakage current. In this work, the two-dimensional (2D) engineering of drain doping profiles is demonstrated to provide significant advantages over conventional (1D) LDD engineering approaches for reducing TFT leakage current. Top-gate n-channel poly-Si TFTs were fabricated on quartz wafers using a conventional high- temperature (950°C) process3. After the formation of the heavily doped (nt) source and drain regions, some wafers were given additional implants at high tilt angles, to form lightly doped (n-) 1D or 2D LDD regions underneath the gate, extending -0.3 pm in from the gate edge. The 1D LDD regions were formed by deep implantation of phosphorus to a dose of 2 x 1013 The 2D LDD regions were formed using a combination of high-angle implants: a deep phosphorus implant (identical to the one used to form the 1D LDD structures), and a shallow counterdoping boron implant to confine the n- LDD region to the bottom region of the channel layer. A 1 hour anneal at 55OOC was used to activate the LDD implants. TFT measurements show that the 1D LDD structure provides a noticeable reduction in leakage com- pared with the standard drain structure, as expected: the median value is reduced from 0.94 pA/pm to 0.61 pA/pm, and the 20%-80% distribution spread is decreased from -16x to xllx. However, substantial further reduction is provided by the 2D LDD structure: the median value is reduced to 0.34 pA/pm and to 0.17 pA/pm with counterdoping boron implant doses of 4x 1OI2 cm-2 and 1 x 1013 cm-2, respectively. (The 20%-80% distribution spreads for the-2D LDD structures are -11 x.) Leakage was confirmed to scale linearly with TFT channel width for the devices fabricated in this work, in order to rule out edge contributions. Numerical device simulations4 indicate that 2D variation of the drain profile can significantly impact lateral electric-field strength Ell in the channel region near the drain: Ellmsx is lowered considerably by moving the extended drain region away from the gate electrode, regardless of the dopant concentration in this region. This technique provides a means for manipulating not only the location hut also the physical extent of the high-field region near the drain. Compared with a conventional LDD structure, a 2D-engineered drain structure can provide substantial improvements in TFT leakage, with more resilience against variations in dopant activation in the extended drain region. In summary, 2D engineering of drain doping profiles provides a significant advantage over conventional 1D engineering approaches for achieving low leakage in poly-Si TFTs. Simulations show that this is due to reductions in the extent and magnitude of the lateral electric field in the channel near the drain.