Fabrication of Low-Temperature Poly-Si Thin Film Transistors with Self-Aligned Graded Lightly Doped Drain Structure

Abstract

A novel approach for fabricating low-temperature poly-Si (LTPS) thin film transistors (TFTs) with self-aligned graded lightly doped drain (LDD) structure was demonstrated. The self-aligned graded LDD structure was formed by side-etching the Al gate under the photoresist followed by excimer laser irradiation for dopant activation and lateral diffusion. The graded LDD poly-Si TFTs exhibited low-leakage-current characteristics without significantly sacrificing driving capability due to the graded dopant distribution in the LDD regions, in which the drain electric field could be reduced. The leakage current of 1 μm graded LDD LTPS TFTs at Vds = 5 V and Vgs = -10 V could reach below 1 pA/μm, and the on/off current ratio at Vds = 5 V exceeded 10 7 .