Anomalous capacitance characteristics of TFTs with LDD structures in the saturation region

Abstract

The effect of lightly doped drain (LDD) doping concentration on the capacitance of a low-temperature polycrystalline silicon (LTPS) thin-film transistor (TFT) is investigated. An anomalous gate-to-source capacitance phenomenon is observed: first, the capacitance decreases, and then it increases according to the gate voltage in the saturation region. This phenomenon is not affected by the subgap density-of-states and arises as the doping concentration of the LDD region is reduced. To investigate the effects of each source and the drain LDD dose on the gate-to-source capacitance, two-dimensional device simulations were conducted in which each dose of the source and drain LDD was changed individually. The reduced controllability of the source voltage to the gate charge in the saturation region due to the increased resistance of the source LDD region with low LDD dose is identified as the reason for this anomalous capacitance phenomenon.