46th Annual Device Research Conference

Abstract

The history and tremendous progress in MOS integrated circuit technology has been dominated by the scaling of device feature size and the increased level of integration. Feature size and integration level have progressed from around 25 pm and 10-100 transistors on a single chip in the mid 1960’s to 0.8 pm and over 4 million transistors in today’s products. The simple conventional MOS transistor was used quite successfully in the successive generations of technologies until the early 1980’s. In the late 1970’s and early 1980’s the continuously decreasing feature size (transistor gate length) combined with limited (step function) decreases in the power supply voltage resulted in sufficiently high electric fields to cause adverse “hot camer” effects. These hot camers degrade MOS transistor performance by increasing interface state density (thus reducing transconductance), and by becoming trapped in the gate dielectric (thus shifting threshold voltage). As a result, a new engineering activity called “drain engineering” arose, and in the early 1980’s, a major change was made in the source/drain structure of the transistor which is most generically known as the LDD (lightly doped drain) transistor today. There are numerous types of LDD structures, but all forms are based on the concept of inserting an intermediate drain doping between the MOS channel and the heavily doped drain region. This serves the purpose to “grade” the drain and drop the drain voltage over a greater distance, thus reducing the high electric fields. As the technology has advanced below 1 pm feature size and