Modeling and characterization of LDD and LDSD NMOS transistors

Abstract

Medium-voltage lateral structures for power NMOS devices, suitable for integration with standard low-voltage CMOS control circuits in power ICs, are presented. Two device types were fabricated on 1.5- mu m micron, N-well, two-metal-layer, 10-mask CMOS standard technology. Design rules and device mask geometry were adapted for enlarging the operating voltage range beyond 5 V. The LDD (lightly doped drain) NMOS transistor is based on the LDD concept. The LDSD (light doped source drain) NMOS transistor applies the same concept to both source and drain terminals. On-resistance as low as 9 m Omega cm/sup 2/ and breakdown voltages of 20 V were experimentally obtained. Monolithic integration of multiple switches with low-voltage control is possible, since structures are electrically compatible. The electric characterization and proposed model for LDD and LDSD NMOS devices in commutation are presented. These structures are aimed at smart power ICs using standard CMOS technologies, for low power applications. Experimental results are presented. >