Abstract
Low temperature polycrystalline silicon thin film transistor (LTPS TFT) has a wide application prospect in flat panel display and other fields due to its higher carrier mobility and better conductivity. Motivated with the development of flat‐panel display devices targeting higher resolution, it is imperative to carry out research in small‐sized LTPS TFT technology. When the channel size is decreased to a certain extent, the effect of the gradual channel approximation is no longer valid. As a result, the short channel effect and the hot carrier effect will have significant impacts on the LTPS TFT devices. To alleviate and eventually to eliminate these two effects, we introduce and implement the Lightly Doped Drain (LDD) structure in the LTPS TFT device. LDD is a technology by adding lightly doped region between source and drain in a TFT, its series resistance is increased, thereby greatly reducing the electric field of drain, resulting in much less hot carrier effect and short channel effect. However, the introduction of LDD structure might have some adverse impacts on the characteristics of LTPS TFT if not optimized. In this paper, we studied the influence of different LDD structures on TFT performance, finding out the optimal LDD structure.
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