Lateral Double-diffused MOSFET Research Articles

Super junction LDMOS with P-trench and stepped buried oxide layer for high performance

In this paper, a new silicon-on-insulator superjunction lateral double-diffused MOSFET (SOI SJLDMOS) with a p-trench layer and stepped buried oxide, is investigated using 3D numerical simulation. The p-trench layer and stepped buried oxide distinguish it from a conventional SOI SJLDMOS. The etched buried oxide layer, with its stepped buried -oxide structure, which facilitates a more even electric field distribution via the electric field modulation effect, increases the breakdown-voltage (BV). Furthermore, the p-trench layer improves the doping concentration through compensation depletion, which further decreases the specific on-resistance (Ron,sp). The simulation indicates that the new device has a higher BV (increased by 29%) than the conventional SOI SJLDMOS. At the same time, Ron,sp decreases by 20% for the on-state for a given drift-region length.

Hot-Carrier Degradation in Power LDMOS: Drain Bias Dependence and Lifetime Evaluation

In this brief, we present an analysis of the degradation induced by hot-carrier stress in new generation power lateral double-diffused MOSFET (LDMOS) transistors. When a relatively high drain voltage is applied during the ON-state regime, high energetic and/or multiple cold electrons are recognized as the main source of degradation affecting the LDMOS lifetime: the latter is usually extrapolated at typical operating drain voltages. Hence, the extrapolation criterion is particularly critical, and different models have been proposed in the past and discussed in this brief. In particular, the dependence of ON-resistance degradation ( $R_{\mathrm{\scriptscriptstyle ON}}$ ) on drain bias is investigated, and a simplified extrapolation model, accounting for the saturation effects of $R_{\mathrm{\scriptscriptstyle ON}}$ at long stress times, is proposed and validated by comparison with experiments and advanced physics-based TCAD simulations, confirming the ability to accurately estimate lifetime on devices featuring short-circuited source–body contacts.

Simulation Study of a p-LDMOS With Double Electron Paths to Enhance Current Capability

In this letter, a p-channel lateral double-diffused MOSFET (p-LDMOS) with double electron paths used to enhance the current capability is proposed. The proposed p-LDMOS has two n-channels that are controlled by an auto-generated voltage signal ( ${V}_{\text {Gn}}$ ). The voltage signal ${V}_{\text {Gn}}$ is generated during the ON and OFF states of the hole current that flows across an integrated resistor ( $R_{\text {p}}$ ) implemented in the P-base region. Thus, the current capability of the p-LDMOS can be significantly enhanced by the introduced electron current. The simulation results show that the current capability of the proposed p-LDMOS can be comparable to that of the n-type triple RESURF technique without any conductivity modulation effect. The power loss of the proposed p-LDMOS is reduced by approximately 78.6% and 15.6% compared with the triple RESURF p-LDMOS and n-LDMOS, respectively, at a rated load current density of $25~\mu \text{A}/\mu \text{m}$ .

Novel lateral double-diffused MOSFET with folded silicon and high-permittivity dielectric breaking silicon limit

A novel folded-accumulation LDMOS (FALDMOS) employing high-permittivity (HK) material as the partial field dielectric (HK-FALDMOS) is proposed and investigated by simulation. The device features the high-k dielectric partially replacing conventional SiO2 as the field oxide covering partial drift region and the gate electrode extending to the drain electrode. In the ON-state, the majority-carrier accumulation effect of HK-FALDMOS is more intense than that of FALDMOS, which is attributed to the larger capacitance of high-k film with the same dielectric thickness. Besides, a higher doping concentration in drift region I is obtained due to the electric field modulation effect resulting from the employed high-k film, which further reduces the specific on-resistance (Ron,sp) of the drift region I. The breakdown voltage (BV) declines slightly with the increase of permittivity of high-k film. Simulation results show that the proposed HK-FALDMOS has best-in-class Ron,sp-BV performance (9.9 mΩ mm2 with BV of 44.9 V when the relative permittivity of high-k is 8), which breaks the silicon limit of LDMOS.

Novel LDMOS Optimizing Lateral and Vertical Electric Field to Improve Breakdown Voltage by Multi-Ring Technology

A novel lateral double-diffused MOSFET with multi-ring substrate (M-R LDMOS) is proposed. New high electric field peaks are introduced by the M-R due to the effect of the electric field modulation, which makes the lateral and vertical electric field distributions more uniform at the same time. As a consequence, the breakdown voltage (BV) of M-R LDMOS is enhanced significantly. The simulation result shows that the BV of M-R LDMOS is 566 V with the drift region length of $30~\mu \text{m}$ . Furthermore, the figure-of-merit of M-R LDMOS is 3.05 MW/cm2, increased by 190%, 45%, and 24.5% in comparison with the conventional LDMOS, the step doping drift LDMOS, and the assisted deplete-substrate layer LDMOS, respectively. M-R LDMOS has a much better performance. In addition, the proposed M-R LDMOS uses the highly doped substrate ( $3\times 10^{15}$ cm−3), which significantly reduces the cost of substrate.

Improvement of Deep-Trench LDMOS With Variation Vertical Doping for Charge-Balance Super-Junction

A design concept of variation vertical doping is proposed to upgrade the deep-trench lateral double-diffused metal–oxide–semiconductor field-effect transistor. Due to the proposal, a drift region in the form of charge-balance super-junction is first gained in such a device. Hence, the relationship between the breakdown voltage and the specific on-resistance is significantly improved. Numerical simulations demonstrate that the proposal is valid to increase the theoretical limit of the figure of merit to be about 44.9 MW/cm $^{\textsf {2}}$ , more than twice of that of the prior art. Besides, a feasible realization method is presented and studied.

Study of the SOI LDMOS With Low Conduction Loss and Less Gate Charge

This brief focuses on the silicon-on-insulator (SOI) split gate (SG) superjunction (SJ) lateral double-diffused MOSFET (LDMOS), in which the p-column is not only utilized to compensate the fields produced by the opposite charges in the drift region, but also further acting as an SG. The accumulation layers of an electron are formed in the drift region during the on-state, providing the lower resistance paths for electric current, which leads to a decrease in the specific on-resistance ( ${R}_{\text {ON,sp}}$ ). Furthermore, because of the semiconductor-insulator-semiconductor (SIS) capacitor, not all of the positive charges in the n-drift region intend to induce the negative charges on the gate, since there is a Miller capacitance, and thus the gate charge ( ${Q}_{G}$ ) is reduced with the weakened Miller effect. The simulation results indicate that comparing with the previous SOI SJ-LDMOS, ${R}_{\text {ON,sp}}$ and ${Q}_{G}$ can be reduced by 35% and 17%, respectively, leading to a 46% improvement of figure of merit for the proposed structure.

A Temperature-Dependent SiC MOSFET Modeling Method Based on MATLAB/Simulink

In this paper, a modeling method based on MATLAB/Simulink for a temperature-dependent SiC MOSFET in the entire working region was proposed. Using a supplementary test circuit, the output characteristics of a device in the saturated region were extracted. Based on these characteristics, the model covered the output characteristics of the device in the whole working region. From the output curves, three main parameters essential for modeling were derived. Based on the Si lateral double-diffused MOSFET model, a temperature-dependent static model of SCT20N120 was established by adding a temperature-dependent compensation voltage source to simulate the temperature characteristics of the threshold voltage and a temperature-dependent compensation current source to compensate for the drain current error in the linear region due to the differences in structure and material between Si and SiC. In addition, based on the gate equivalent circuit, the dynamic model of the target device was established. The temperature-dependent static simulation results could simulate the actual measured values well. Furthermore, based on the comparison between the dynamic simulation results involving the device’s turn-ON and turn-OFF process losses and the actual transient state losses derived from a double-pulse test under the conditions of $V_{\mathrm{ ds}}=300$ V, $I_{d}=15$ A, $R_{g\_{}exton}=18\,\,\Omega $ , and $R_{g\_{}extoff}=12\,\,\Omega $ at 200 °C, the maximum error was 6.7%.

An Improved SOI P-Channel LDMOS With High- ${k}$ Gate Dielectric and Dual Hole-Conductive Paths

An improved p-channel lateral double-diffused MOSFET (pLDMOS) with silicon-on-insulator substrate is proposed. On one hand, the improvement is attributed to a dielectric film with high permittivity (high-k), which is employed at the silicon surface to optimize the electric field distribution. Thus, the drift region dose could be increased, while its deviation has less influence on the breakdown voltage (BV). On the other hand, an additional pLDMOS is introduced to form another hole current path, which contributes to a decreased specific ON-resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> ). The simulation results show that the proposed structure exhibits a BV of 366 V and an Ron,sp of 24 mΩ·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , at a back gate bias of -200 V. Compared with the previous one, R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> is decreased by 39%, and the dose deviation window of the drift region for ensuring the breakdown voltage above 300 V is relaxed from ±2% to ±5%.

Ultra-low specific on-resistance 700V LDMOS with a buried super junction layer

An ultra-low specific on-resistance 700 V lateral double-diffused MOSFET (LDMOS) with a buried super junction (BSJ) layer is proposed. [1–9] Buried P-pillars in the LDMOS can be depleted by neighboring N-pillars, overlying and underlying N-drift regions simultaneously, thus allowing a higher doping concentration. Consequently, the doping concentration of either the N-drift regions or N-pillars, or both, may also be increased therewith to compensate the surplus charges in the P-pillars. Compared with conventional surface super junction (SSJ) LDMOS, in which the super junction layer is implemented at the upper surface of the drift region, and P-pillars can only be depleted by the adjacent N-pillars and the N-drift regions beneath, the proposed novel LDMOS structure may have a lower specific on-resistance (Ron,sp) while maintain the same breakdown voltage (BV). Simulation results indicate that the Ron,sp of the novel structure is only 80.5 mΩ cm2 with a high BV of 750 V, which is reduced by 17% in comparison with the Ron,sp of a conventional SSJ LDMOS.

Novel Superjunction LDMOS (&gt;950 V) With a Thin Layer SOI

A novel superjunction (SJ) lateral double-diffused MOSFET (>950 V) with a thin layer SOI combining the advantage of low specific on-resistance ${R}_{\text {on,sp}}$ of the SJ and the high breakdown voltage ${V}_{\text {B}}$ of the thin SOI is proposed and experimentally demonstrated in this letter. Based on our previously developed equivalent substrate model, the optimized SJ endows the device with a respectably reduced ${R}_{\text {on,sp}}$ without sacrificing ${V}_{\text {B}}$ . Meanwhile, the thin layer SOI is designed with the enhanced dielectric layer field principle to carry out a high ${V}_{\text {B}}$ . The experimental results exhibit a ${R}_{\text {on,sp}}$ of 145 $\text{m}\Omega \cdot $ cm2 with a ${V}_{\text {B}}$ of 977 V. This represents a reduction in ${R}_{\text {on,sp}}$ by 18.1% when compared with the theoretical ${R}_{\text {on,sp}} \propto {V}_{\text {B}}^{{2.5}}\vphantom {^{^{^{^{}}}}}$ “silicon limit”.

Controlled Kink Effect in a Novel High-Voltage LDMOS Transistor by Creating Local Minimum in Energy Band Diagram

A new technique to control the kink effect in the high-voltage lateral double-diffused MOSFET (LDMOS) is presented in this paper. This technique produces a local minimum in the band diagram of the proposed structure, which causes the lower barrier height for the holes from the channel to the source region. So, the produced excess holes during the impact ionization process in the channel are reduced significantly. We have called the proposed structure as local minimum energy band LDMOS (LMEB-LDMOS) transistor. The LMEB-LDMOS structure contains modified source and drain regions. The modified source region creates a local minimum in the energy band diagram for absorbing the excess holes, and the modified drain region causes high breakdown voltage (462 V) and low specific on-resistance ( $5.1~\text {m}\Omega \cdot ~\text {cm}^{{{{2}}}})$ . Also, the drift region with lower doping density than drain is deleted in LMEB-LDMOS transistor. The simulation with 2-D ATLAS simulator shows that the proposed structure improves the device performance.

PSOI pLDMOS with n‐buried layer

Partial-silicon (Si)-on-insulator p-channel lateral double-diffused metal–oxide–semiconductor field-effect transistor with n-buried layer (NBL PSOI pLDMOS) is proposed. One feature of the device is an Si window under the drain offers a heat conduction path to alleviate the self-heating effect. Meanwhile, a fully depleted NBL on the bottom surface of the Si layer provides a large amount of ionised donors to enhance the electric field of the buried oxide (BOX) layer. The NBL can prevent the substrate leakage phenomenon of the PSOI pLDMOS. There is a triple reduced surface field structure in the p-drift region. Some equipotential lines spread into the p-substrate through the Si window. Furthermore, the assistant depletion caused by the NBL increases the p-drift region concentration, which achieves a lower specific on-resistance (R on,sp). With 20 µm p-drift region length and 1 µm BOX thickness, the NBL PSOI pLDMOS obtains a higher breakdown voltage (BV) of 289 V, which is increased by 88.9 and 43.8% compared with the Con SOI and NBL SOI pLDMOS, respectively. The R on,sp is decreased by 82.3 and 17.2%, respectively. The figure of merit (FOM = BV2/R on,sp) is 1.65 MW cm−2. A lower maximum surface temperature of 312.3 K is obtained.

Simulation-Based Study of Hybrid Fin/Planar LDMOS Design for FinFET-Based System-on-Chip Technology

A hybrid fin/planar lateral double-diffused MOSFET (LDMOS) design (hybrid FET) is proposed for the high-voltage input–output devices in a FinFET-based system-on-chip (SoC) technology. 3-D technology computer-aided design simulations show that a planar drift region and a planar drain region are advantageous for higher breakdown voltage (BV) to specific on-state resistance ( ${R}_{\text {on$\_{}$sp}})$ ratio (BV2/ ${R}_{\text {on$\_{}$sp}})$ . By slightly extending the planar portion of the semiconductor active region into the gated channel region, the theoretical limit of BV2/ ${R}_{\text {on$\_{}$sp}}$ for LDMOS can be surpassed. Hybrid FETs can be fabricated using a process flow that is compatible with the state-of-art FinFET SoC technology.

An ultra-low specific on-resistance double-gate trench SOI LDMOS with P/N pillars

A novel ultra-low specific on-resistance (Ron,sp) trench lateral double-diffused MOSFET with P/N pillars and dual trench gates (P/N DTG-T LDMOS) based on silicon-on-insulator technology is proposed in this paper. The new structure features dual trench gates and heavily doping P/N pillars. The P/N pillars are inserted into the drift region under the P-well. The P-pillar causes an assistant depletion effect on the drift region. The N-pillar can not only improve the breakdown voltage (BV) by modulating the electric field but also significantly reduce the Ron,sp by increasing the doping concentration of the drift region. Furthermore, the dual trench gates form dual conduction channels and the heavily doping N-pillar provides a lower resistance region for the carriers, which can both reduce the Ron,sp. Consequently, compared with the conventional trench LDMOS, a lower Ron,sp of 0.58 mΩ cm2 and a higher the figure of merit (FOM, FOM=BV2/Ron,sp) of 62.9 MW/cm2 are obtained for the P/N DTG-T LDMOS, which are improved by 74.8% and 308.4% respectively. Meanwhile, the BVs of the both structures are maintained at a same level of 190 V.

Numerical Investigation of High-Voltage Partial Buried P/N-Layer SOI LDMOS

High-voltage lateral double-diffused MOSFETs with partial buried P/N-type silicon layers (PBPL/PBNL) in silicon-on-insulator (SOI) technology are investigated numerically. In the lateral direction, the partial buried silicon layer (PBL) can introduce an additional electric field peak, which improves the surface electric field distribution and increases the charge accommodation in the drift region. Consequently, in the vertical direction, PBPL and PBNL can both induce higher electric field into the buried-oxide layer, and thus enhance the breakdown voltage (BV) significantly. Due to the higher electron concentration in the drift region, the ON-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}}$ ) can be also reduced remarkably. The 2-D simulation results show that PBPL and PBNL SOIs can achieve BVs of 296 and 365 V, respectively, in comparison to the conventional SOI (BV ~ 225 V) and the buried N-layer SOI (BV ~ 231 V). In addition, by comparison with the conventional SOI, ${R}_{ \mathrm{\scriptscriptstyle ON}}$ can be reduced about 31.7% and 13.8% for PBPL and PBNL SOIs, respectively. Finally, hybrid PBPL/PBNL SOIs are studied and shown to be capable of further improving the device performance.

Multiple Trench Split-gate SOI LDMOS Integrated With Schottky Rectifier

In this paper, a multiple trench split-gate silicon-on-insulator (SOI) lateral double-diffused MOSFET with a Schottky rectifier (MTS-SG-LDMOS) is proposed and its characteristics are studied using 2-D simulations. The new structure features double oxide trenches, a floating polysilicon split-gate, and a Schottky rectifier. Each oxide trench includes a vertical field plate which enhances the depletion of the drift region and modulates the bulk electric field. As the simulation results, when compared to the conventional SOI LDMOS (C-LDMOS), the breakdown voltage in the MTS-SG-LDMOS increases from 297 to 350 V, the specific on-state resistance ( ${R} _{ \mathrm{\scriptscriptstyle ON},\mathsf {sp}}$ ) decreases from 142.9 to 48.2 $\text{m}\Omega \cdot \mathsf {cm}^{{\mathsf {2}}}$ , and the gate–drain charge ( ${Q} _{{\mathsf {gd}}}$ ) decreases from 19 to 9 pC. Moreover, the reverse recovery time of the proposed structure shows a 73.6% reduction as compared to the C-LDMOS device.

SOI LDMOSFET with Up and Down Extended Stepped Drift Region

To increase the breakdown voltage and decrease the ON resistance, a silicon-on-insulator (SOI) lateral double-diffused metal–oxide–semiconductor field-effect transistor (LDMOSFET) in which the drift region extends to the up and down oxides in a step shape is proposed. This up and down extended stepped drift SOI (UDESD-SOI) structure demonstrates a modified lateral electric field distribution with additional peaks as well as a decrease of the usual peaks near the drain and gate. Two-dimensional (2D) simulations were used to compare the characteristics of the proposed UDESD-SOI structure with those of other structures, viz. down extended stepped drift SOI (DESD-SOI), up extended stepped drift SOI (UESD-SOI), and conventional SOI (C-SOI). Under the same conditions, the breakdown voltage of the UDESD-SOI structure was nearly 35%, 117%, and 318% higher compared with the DESD-SOI, UESD-SOI, and C-SOI structure, respectively. To determine the optimum parameters for the UDESD-SOI structure leading to the highest breakdown voltage, a comparative study was performed to investigate the effect of the doping concentration in the drift region, buried oxide (BOX) thickness, and thickness of up and down extended steps (T 1 and T 2, respectively). In addition, the drain current (ON resistance) of the UDESD-SOI structure was found to be 13%, 43%, and 229% higher (16%, 65%, and 257% lower) than the values for the DESD-SOI, UESD-SOI, and C-SOI structure, respectively.

An improved SOI LDMOS with buried field plate

A silicon-on-insulator (SOI) lateral double-diffused MOSFET (LDMOSFET) with a buried field plate (BFP-LDMOS) is proposed. Its characteristics are studied using 2-D simulations. The proposed structure features double buried field plates which are surrounded by buried oxide (BOX) and connected to the source and drain electrode, respectively. The drain buried field plate (DBFP) prevents a premature breakdown at the interface of the silicon/BOX and enhances the dielectric field. The source buried field plate (SBFP) introduces a new electric-field peak and modulates the distribution of the horizontal electric field. In addition, the BFPs replace part of the BOX, which is useful to minimize self-heating effects (SHE). According to the simulation results, compared to a conventional SOI LDMOS (C-LDMOS), the breakdown voltage (BV) in the BFP-LDMOS increases from 128 V to 182 V. The specific on-state resistance (Ron,sp), however, decreases from 20.46 mΩ cm2 to 18.50 mΩ cm2. Moreover, the maximum lattice temperature at 1 mW/μm and Vgs = 10 V is reduced by 33.8 K compared to the C-LDMOS device.

New superjuction LDMOS with surface and bulk electric field modulation by buffered step doping and multi floating buried layers

A new superjunction lateral double diffused MOSFET with surface and bulk electric field modulation (SBEFM SJ-LDMOS) by applying of multiple floating buried layers and buffered step doping is proposed in this paper. The Multiple N-type floating buried layers are embedded in P-substrate, to reduce the amount of field crowding at N+/N-buffer/P-substrate junction by spreading the vertical depletion layer, which effectively improves the bulk electric field distribution in SJ-LDMOS, and the N+/N-buffer/P-substrate junction and the auxiliary MFB layers/substrate junctions jointly sustain a high vertical breakdown voltage (BV). In addition, based on the buffered step doping layer under the SJ layer, a uniform lateral electric field at the drift region surface of the device is obtained. Therefore, the bulk and surface electric field are both optimized simultaneously in SBEFM SJ-LDMOS. Simulated results show that compared with the conventional Buffered SJ-LDMOS and BSD SJ-LDMOS, the proposed SBEFM SJ-LDMOS improves BV by 131.7% and 80.4%, respectively, at the same drift region length and with low specific ON-resistance (RON,sp). SBEFM SJ-LDMOS exhibits excellent performance with the power figure-of-merit (FOM=BV2/RON,sp) of 13.07 MW/cm2.